W83637HF_06 Datasheet, PDF (87/151 Pages) Winbond – LPC I/O

W83637HF/HG
7.2 Register File
Complete register file table
Bit Number
Register file
Abbr. 7
6
5
4
3
2
1
0
Base + 0 ^{Receiver Buffer}
BDLAB = 0
Register (Read
only)
RBR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Base + 0 ^{Transmitter Buffer}
BDLAB = 0
Register (Write
only)
TBR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Base + 1
Interrupt Enable
Register
IER
BDLAB = 0
default
SCC8
x
SCC4
x
SCC8_IO SCC4_IO ESCPTI
(note) (note) (note)
0
0
0
ESCSRI
(note)
0
ETBREI
(note)
0
ERDRI
(note)
0
Base + 2
BDLAB = 0
Interrupt Status
Register (Read
only)
ISR
FIFO
enabled
FIFO
enabled
SCPSNT
SCPTI
(note)
INTS2
(note)
INTS1
(note)
INTS0 _Interrupt
(note) ^pending
Base + 2
BDLAB = 0
Smart Card FIFO
control Register
(Write only) ^SCFR
default
RxTL1
(note)
0
RxTL0
(note)
0
TxFRST RxFRST
Reserved Reserved Reserved
(note) (note)
x
x
x
0
0
Enable
FIFO
0
Base + 3
Smart Card
Control
Register
BDLAB
EPE
Reserved Reserved
SCCR (note)
(note)
PBE
Reserved Reserved SC_SEL
(note)
default
0
x
x
0
0
x
x
0
Base + 4
Clock Base
Register
Bit 7
CBR
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
default
0
0
0
0
1
1
0
0
Base + 5
Smart Card
Status
Register (Read
only)
SCSR
RxFEI
(note)
TSRE
(note)
TBRE
(note)
SBD
(note)
NSER
(note)
PBER
(note)
OER
(note)
RDR
(note)
Base + 6
Guard Time
Register
Bit 7
GTR
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
default
0
0
0
0
0
0
0
1
Extended Control
Base + 7
Register
ECR
Cold
reset
SCKFS1 SCKFS0 CLKSTPL CLKSTP SCIODIR
Reserved
(note) (note) (note) (note) (note)
Warm
reset
default
0
x
0
1
0
0
1
0
Base + 0
Baud rate divisor
Latch Lower byte _BLL
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BDLAB = 1
default
0
0
0
1
1
1
1
1
Base + 1
Baud rate divisor
Latch Higher byte _BLH
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
BDLAB = 1
default
0
0
0
0
0
0
0
0
Base + 2
BDLAB = 1
Smart Card ID
number (Read
only)
0
1
1
1
0
0
0
0
- 82 -
Publication Release Date: March, 2006
Revision 1.6