W25Q128FVSIF-TR Datasheet, PDF (87/100 Pages) Winbond – 3V 128M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI

W25Q128FV
AC Electrical Characteristics (cont‟d)
DESCRIPTION
SPEC
SYMBO
A
UNI
L
LT
MI
TY
MAX
T
N
P
/HOLD to Output Low-Z
tHHQX⁽²⁾
tLZ
7
ns
/HOLD to Output High-Z
tHLQZ⁽²⁾
tHZ
12
ns
Write Protect Setup Time Before /CS Low
tWHSL⁽³⁾
20
ns
Write Protect Hold Time After /CS High
tSHWL⁽³⁾
100
ns
/CS High to Power-down Mode
/CS High to Standby Mode without ID Read
tDP⁽²⁾
tRES1⁽²⁾
3
µs
3
µs
/CS High to Standby Mode with ID Read
/CS High to next Instruction after Suspend
tRES2⁽²⁾
tSUS⁽²⁾
1.8
µs
20
µs
/CS High to next Instruction after Reset
tSUS⁽²⁾
/RESET pin Low period to reset the device
tRST⁽²⁾⁽⁵⁾
1
30
µs
µs
Write Status Register Time
Byte Program Time (First Byte) ⁽⁴⁾
Additional Byte Program Time (After First Byte) ⁽⁴⁾
Page Program Time
Sector Erase Time (4KB)
Block Erase Time (32KB)
W25Q128FVxxIG
W25Q128FVxxIQ
W25Q128FVxxIF
Block Erase Time (64KB)
Chip Erase Time
tW
t_BP1(4)
t_BP2(4)
tPP
tSE
tBE₁
tBE₂
tCE
10
15
ms
30
50
µs
2.5
12
µs
0.7
3
ms
100
400
ms
45
120
1,600
ms
150
2,000
ms
40
200
s
Notes:
1.Clock high + Clock low must be less than or equal to 1/fC.
2.Value guaranteed by design and/or characterization, not 100% tested in production.
3.Only applicable as a constraint for a Write Status Register instruction when SRP[1:0]=(0,1).
4.For multiple bytes after first byte within a page, tBPN = tBP1 + tBP2 * N (typical) and tBPN = tBP1 + tBP2 * N (max), where N = number
of bytes programmed.
5.It‟s possible to reset the device with shorter tRESET (as short as a few hundred ns), a 1us minimum is recommended to ensure
reliable operation.
6.4-bytes address alignment for QPI/Quad Read
- 86 -
Publication Release Date: October 09, 2013
Revision I