W25Q128FVSIF-TR Datasheet, PDF (57/100 Pages) Winbond – 3V 128M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI

W25Q128FV
8.2.20 Chip Erase (C7h / 60h)
The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write
Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status
Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the
instruction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in Figure 34.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase
instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction will
commence for a time duration of tCE (See AC Characteristics). While the Chip Erase cycle is in
progress, the Read Status Register instruction may still be accessed to check the status of the BUSY
bit. The BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is
ready to accept other instructions again. After the Chip Erase cycle has finished the Write Enable Latch
(WEL) bit in the Status Register is cleared to 0. The Chip Erase instruction will not be executed if any
memory region is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits or the
Individual Block/Sector Locks.
/CS
CLK
Mode 3
Mode 0
DI
(IO₀)
DO
(IO₁)
0 1 2 3 4 5 6 7 Mode 3
Mode 0
Instruction (C7h/60h)
High Impedance
/CS
CLK
IO₀
Mode 3
Mode 0
01
Instruction
C7h/60h
Mode 3
Mode 0
IO₁
IO₂
IO₃
Figure 34. Chip Erase Instruction for SPI Mode (left) or QPI Mode (right)
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Publication Release Date: October 09, 2013
Revision I