W25Q128FVSIG_13 Datasheet, PDF (85/97 Pages) Winbond – 3V 128M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI

W25Q128FV
9.7 AC Electrical Characteristics (cont’d)
DESCRIPTION
/HOLD Active Hold Time relative to CLK
SYMBOL ALT
MIN
tCHHH
5
SPEC
TYP
MAX
UNIT
ns
/HOLD Not Active Setup Time relative to CLK
tHHCH
5
ns
/HOLD Not Active Hold Time relative to CLK
/HOLD to Output Low-Z
/HOLD to Output High-Z
Write Protect Setup Time Before /CS Low
Write Protect Hold Time After /CS High
/CS High to Power-down Mode
/CS High to Standby Mode without ID Read
/CS High to Standby Mode with ID Read
/CS High to next Instruction after Suspend
/CS High to next Instruction after Reset
/RESET pin Low period to reset the device
tCHHL
5
tHHQX⁽²⁾
tLZ
tHLQZ⁽²⁾
tHZ
tWHSL⁽³⁾
20
tSHWL⁽³⁾
100
tDP⁽²⁾
tRES1⁽²⁾
tRES2⁽²⁾
tSUS⁽²⁾
tRST⁽²⁾
tRESET⁽²⁾
1⁽⁵⁾
ns
7
ns
12
ns
ns
ns
3
µs
3
µs
1.8
µs
20
µs
30
µs
µs
Write Status Register Time
tW
Byte Program Time (First Byte) ⁽⁴⁾
t_BP1
Additional Byte Program Time (After First Byte) ⁽⁴⁾
t_BP2
Page Program Time
tPP
10
15
ms
30
50
µs
2.5
12
µs
0.7
3
ms
Sector Erase Time (4KB)
tSE
100
400
ms
Block Erase Time (32KB)
Block Erase Time (64KB)
Chip Erase Time
tBE₁
120
1,600
ms
tBE₂
150
2,000
ms
tCE
40
200
s
Notes:
1.
2.
3.
4.
5.
6.
Clock high + Clock low must be less than or equal to 1/fC.
Value guaranteed by design and/or characterization, not 100% tested in production.
Only applicable as a constraint for a Write Status Register instruction when SRP[1:0]=(0,1).
For multiple bytes after first byte within a page, t_BPN = t_{BP1 +} t_{BP2 * N} (typical) and t_BPN = t_{BP1 +} t_{BP2 * N} (max), where N =
number of bytes programmed.
It is possible to reset the device with shorter tRESET (as short as a few hundred ns), a 1us minimum is recommended to
ensure reliable operation.
Tested on sample basis and specified through design and characterization data. TA = 25° C, VCC = 3.0V, 25% driver
strength.
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Publication Release Date: October 01, 2012
Revision D