W78C52D Datasheet, PDF (8/18 Pages) Winbond – 8-BIT MICROCONTROLLER

Preliminary W78C52D
The time-out period is obtained using the following formula:
1 _{× 214 × PRESCALER ×1000 ×12 mS}
OSC
Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6
(CLRW). After 1 is written to this bit, the 14-bit timer , prescaler and this bit will be reset on the next
instruction cycle. The Watchdog timer is cleared on reset.
WIDL
IDLE
OSC
1/12
ENW
EXTERNAL
RESET
PRESCALER
14-BIT TIMER
CLEAR
INTERNAL
RESET
Watchdog Timer Block Diagram
CLRW
Typical Watchdog time-out period when OSC = 20 MHz
PS2 PS1 PS0
00 0
01 0
00 1
01 1
10 0
10 1
11 0
11 1
WATCHDOG TIME-OUT PERIOD
19.66 mS
39.32 mS
78.64 mS
157.28 mS
314.57 mS
629.14 mS
1.25 S
2.50 S
Reduce EMI Emission
Because of the on-chip ROM, when a program is running in internal ROM space, the ALE will be
unused. The transition of ALE will cause noise, so it can be turned off to reduce the EMI emission if it
is not needed. Turning off the ALE signal transition only requires setting the bit 0 of the AUXR SFR,
which is located at 08Eh. When ALE is turned off, it will be reactivated when the program accesses
external ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off
again after it has been completely accessed or the program returns to internal ROM code space.
AUXR - Auxiliary Register
Bit:
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
AO
Mnemonic: AUXR
AO: Turn off ALE signal.
Address: 8Eh
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