W78C52D Datasheet, PDF (6/18 Pages) Winbond – 8-BIT MICROCONTROLLER

Preliminary W78C52D
deglitch the reset line when the W78C52D is used with an external RC network. The reset logic also
has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are
initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the
other SFR registers except SBUF to 00H. SBUF is not reset.
New Defined Peripheral
In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupts
INT2 , INT3 have been added to either the PLCC or QFP package. And description follows:
1. INT2 / INT3
Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external
interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are
determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register
is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To
set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example,
"SETB 0C2H" sets the EX2 bit of XICON.
***XICON - external interrupt control (C0H)
PX3
EX3
IE3
IT3
PX2
EX2
IE2
IT2
PX3: External interrupt 3 priority high if set
EX3: External interrupt 3 enable if set
IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced
IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software
PX2: External interrupt 2 priority high if set
EX2: External interrupt 2 enable if set
IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced
IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software
Eight-source interrupt informations:
INTERRUPT
SOURCE
External Interrupt 0
Timer/Counter 0
External Interrupt 1
Timer/Counter 1
Serial Port
Timer/Counter 2
External Interrupt 2
External Interrupt 3
VECTOR
ADDRESS
03H
0BH
13H
1BH
23H
2BH
33H
3BH
POLLING
SEQUENCE WITHIN
PRIORITY LEVEL
ENABLE
REQUIRED
SETTINGS
0 (highest)
IE.0
1
IE.1
2
IE.2
3
IE.3
4
IE.4
5
IE.5
6
XICON.2
7 (lowest)
XICON.6
INTERRUPT
TYPE
EDGE/LEVEL
TCON.0
-
TCON.2
-
-
-
XICON.0
XICON.3
-6-