W78C52D Datasheet, PDF (12/18 Pages) Winbond – 8-BIT MICROCONTROLLER

Preliminary W78C52D
Data Read Cycle
PARAMETER
SYMBOL
ALE Low to RD Low
TDAR
RD Low to Data Valid
TDDA
Data Hold from RD High
TDDH
Data Float from RD High
TDDZ
RD Pulse Width
TDRD
Notes:
1. Data memory access time is 8 TCP.
2. "∆" (due to buffer driving delay and wire loading) is 20 nS.
MIN.
3 TCP-∆
-
0
0
6 TCP-∆
TYP.
-
-
-
-
6 TCP
MAX.
3 TCP+∆
4 TCP
2 TCP
2 TCP
-
UNIT
nS
nS
nS
nS
nS
NOTES
1, 2
1
2
Data Write Cycle
PARAMETER
SYMBOL MIN.
ALE Low to WR Low
Data Valid to WR Low
Data Hold from WR High
WR Pulse Width
TDAW
TDAD
TDWD
TDWR
3 TCP-∆
1 TCP-∆
1 TCP-∆
6 TCP-∆
Note: "∆" (due to buffer driving delay and wire loading) is 20 nS.
TYP.
-
-
-
6 TCP
MAX.
3 TCP+∆
-
-
-
UNIT
nS
nS
nS
nS
Port Access Cycle
PARAMETER
Port Input Setup to ALE Low
Port Input Hold from ALE Low
Port Output to ALE
SYMBOL
TPDS
TPDH
TPDA
MIN.
1 TCP
0
1 TCP
TYP.
-
-
-
MAX.
-
-
-
UNIT
nS
nS
nS
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to
ALE, since it provides a convenient reference.
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