W39L040A Datasheet, PDF (8/26 Pages) Winbond – 512K × 8 CMOS FLASH MEMORY

W39L040A
same time (see "Feature"). The system is not required to provide any controls or timings during these
operations.
The automatic erase begins on the rising edge of the last #WE pulse in the command sequence and
terminates when the data on DQ7 is "1" at which time the device returns to read the mode.
Refer to the Erase Command Flow Chart using typical command strings and bus operations.
6.3.5 Sector Erase Command
Sector erase is a six-bus-cycle operation. There are two "unlock" write cycles, followed by writing the
"set-up" command. Two more "unlock" write cycles then follows by the sector erase command. The
sector address (any address location within the desired sector) is latched on the falling edge of #WE,
while the command (30H) is latched on the rising edge of #WE.
Sector erase does not require the user to program the device prior to erase. When erasing a sector or
sectors the remaining unselected sectors are not affected. The system is not required to provide any
controls or timings during these operations.
The automatic sector erase begins after the erase command is completed, right from the rising edge
of the #WE pulse for the last sector erase command pulse and terminates when the data on DQ7,
#Data Polling, is "1" at which time the device returns to the read mode. #Data Polling must be
performed at an address within any of the sectors being erased.
Refer to the Erase Command flow Chart using typical command strings and bus operations.
6.4 Write Operation Status
6.4.1 DQ7: #Data Polling
The W39L040A device features #Data Polling as a method to indicate to the host that the embedded
algorithms are in progress or completed.
During the Embedded Program Algorithm, an attempt to read the device will produce the complement
of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to
read the device will produce the true data last written to DQ7.
During the Embedded Erase Algorithm, an attempt to read the device will produce a "0" at the DQ7
output. Upon completion of the Embedded Erase Algorithm, an attempt to read the device will produce
a "1" at the DQ7 output.
For chip erase, the #Data Polling is valid after the rising edge of the sixth pulse in the six #WE write
pulse sequences. For sector erase, the #Data Polling is valid after the last rising edge of the sector
erase #WE pulse. #Data Polling must be performed at sector addresses within any of the sectors
being erased. Otherwise, the status may not be valid.
Just prior to the completion of Embedded Algorithm operations DQ7 may change asynchronously
while the output enable (#OE) is asserted low. This means that the device is driving status information
on DQ7 at one instant of time and then that byte′s valid data at the next instant of time. Depending on
when the system samples the DQ7 output, it may read the status or valid data. Even if the device has
completed the Embedded Algorithm operations and DQ7 has a valid data, the data outputs on DQ0 –
DQ6 may be still invalid. The valid data on DQ0 − DQ7 will be read on the successive read attempts.
The #Data Polling feature is only active during the Embedded Programming Algorithm, Embedded
Erase Algorithm, or sector erase time-out (see "Command Definitions").
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