W39L040A Datasheet, PDF (16/26 Pages) Winbond – 512K × 8 CMOS FLASH MEMORY

W39L040A
AC Characteristics, continued
7.4.3 Read Cycle Timing Parameters
(VDD = 3.0 ~ 3.6V for 70 nS or VDD = 2.7 ~ 3.6V for 90 nS, VSS = 0V, TA = 0 to 70° C)
PARAMETER
SYM.
70 nS
MIN.
MAX.
Read Cycle Time
TRC
70
-
Chip Enable Access Time
TCE
-
70
Address Access Time
TAA
-
70
Output Enable Access Time
TOE
-
30
#CE High to High-Z Output
TCHZ
-
16
#OE High to High-Z Output
TOHZ
-
16
Output Hold from Address Change
TOH
0
-
90 nS
MIN. MAX.
90
-
-
90
-
90
-
35
-
16
-
16
0
-
UNIT
nS
nS
nS
nS
nS
nS
nS
7.4.4 Erase/Program Cycle Timing Parameters
PARAMETER
Write Cycle Time
Address Setup Time
Address Hold Time
#CE Setup Time
#CE Hold Time
#OE Setup Time
#WE Pulse Width
#WE High Width
Data Setup Time
Data Hold Time
Byte Programming Time
Chip Programming Time
Chip Erase Cycle Time
Sector Erase Cycle Time
SYM.
TWC
TAS
TAH
TCS
TCH
TOES
TWP
TWPH
TDS
TDH
TBP
TCP
TEC
TEP
MIN.
70
0
45
0
0
0
35
30
35
0
-
-
-
-
70 nS
TYP.
-
-
-
-
-
-
-
-
-
-
9
4.5
6
0.7
MAX.
-
-
-
-
-
-
-
-
-
-
200
13.5
50
6
MIN.
90
0
45
0
0
0
35
30
45
0
-
-
-
-
90 nS
TYP.
-
-
-
-
-
-
-
-
-
-
9
4.5
6
0.7
Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL.
MAX.
-
-
-
-
-
-
-
-
-
-
200
13.5
50
6
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
μS
S
S
S
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