W682510_05 Datasheet, PDF (7/35 Pages) Winbond – DUAL-CHANNEL VOICEBAND CODECS

W682510/W682310
6. PIN DESCRIPTION
Pin
Name
V_REF
Pin #
SSOP
PDIP
1
Pin #
SOP
1
Functionality
(CH1 = Channel 1, CH2 = Channel 2)
This pin is used to bypass the signal ground. It needs to be decoupled to V_SS
through a 0.1 μF ceramic decoupling capacitor. No external loads should be
tied to this pin.
RO2
2
2
CH2 Non-Inverting output of the receive smoothing filter. This pin can typically
drive a 600 Ω load (W682510) or 1200 Ω load (W682310).
RO1
3
4
CH1 Non-Inverting output of the receive smoothing filter. This pin can typically
drive a 600 Ω load (W682510) or 1200 Ω load (W682310)..
PUI
4
PCMMS 5
5
Power up input signal. When this pin is HIGH (tied to V_DD) the part is powered
up. When LOW (tied to V_SS) the part is powered down.
6
PCM mode select input (serial or parallel data interface) HIGH = Parallel, LOW
= Serial
VDD
6
8
Power supply. This pin should be decoupled to V_SS with a 0.1μF ceramic
capacitor.
VSSD
7
9
This is the digital supply ground. This pin should be connected to 0V.
FSR
8
10 _{8 kHz Frame Sync input for the PCM receive section. It can also be connected}
to the FST pin when transmit and receive are synchronous operations.
PCMR2
9
11 _{CH2 PCM input data receive pin. The data needs to be synchronous with the}
FSR and BCLK pins.
PCMR1
10
12 _{CH1 PCM input data receive pin. The data needs to be synchronous with the}
FSR and BCLK pins.
PCMT1
11
13 _{CH1 PCM output data transmit pin. The output data is synchronous with the}
FST and BCLK pins.
PCMT2
12
14 _{CH2 PCM output data transmit pin. The output data is synchronous with the}
FST and BCLK pins.
FST
13
15 _{8 kHz transmit frame sync input. This pin synchronizes the transmit data bytes.}
BCLK
14
16 _{PCM transmit and receive bit clock input pin for CH1 and CH2 transmit.}
VSSA
15
18 _{This is the analog supply ground. This pin should be connected to 0V.}
μ/A-Law 16
AI1
17
19 _{Compander mode select pin. μ-Law companding is selected when this pin is}
LOW (tied to V_SS.) A-Law companding is selected when pin is HIGH (tied to
V_DD.)
21 _{CH1 Non-Inverting input of the first gain stage in the transmit path.}
AO1-
18
22 _{CH1 Inverting analog output of the first gain stage in the transmit path.}
AO2-
19
23 _{CH2 Inverting analog output of the first gain stage in the transmit path}
AI2
20
24 _{CH2 Non-Inverting input of the first gain stage in the transmit path.}
Publication Release Date: April 2005
-7-
Revision A10