W682510_05 Datasheet, PDF (13/35 Pages) Winbond – DUAL-CHANNEL VOICEBAND CODECS

W682510/W682310
7.4.2. BCLK
This is the shift clock signal input for the PCMR1, PCMR2, PCMT1, and PCMT2 signals. The
frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, 2048 or
200 kHz. Setting this signal to a steady logic “1” or “0” sets both transmit and receive circuits to the
power saving state.
7.4.3. FSR
This is the receive synchronizing signal input. The required eight-bits of PCM data are selected from
the PCM data signal to the PCMR1 and PCMR2 pins by the receive synchronizing signal. All timing
signals in the receive section are synchronized by this synchronizing signal. This signal must be in
phase with the BCLK. The frequency should be 8 kHz ± 50 ppm to guarantee the AC characteristics.
This device can operate in the range of 6 kHz to 9 kHz, but the electrical characteristics specified in
the data sheet are not guaranteed.
7.4.4. FST
The transmit synchronizing signal input. The PCM output signal from PCMT1 and PCMT2 is sent in
synchronization with this transmit synchronizing signal. This FST signal triggers the PLL and
synchronizes all timing signals of the transmit section. The synchronizing signal must be in phase with
BCLK. The frequency should be 8 kHz ± 50 ppm to guarantee the AC characteristics. This device can
operate in the range of 6 kHz to 9 kHz sample rates, but the electrical characteristics are not
guaranteed. Setting this signal to logic HIGH or LOW drives both transmit and receive circuits to
power saving state.
7.4.5. PCMMS
The control signal for mode selection of the PCM input and output. When this signal is HIGH, the PCM
input and output are in the parallel mode. The PCM data of CH1 and CH2 is input to PCMR1 and
PCMR2, and output from PCMT1 and PCMT2, with the same timing. When this signal is at a LOW
level, the PCM input and output are in the serial mode. The PCM data of CH1 and CH2 is input to
PCMR2 and output from PCMT1 as two serial 8-bit bytes.
7.5. POWER STATE MODES
7.5.1. Power Save Mode
In the power save mode, all internal analog circuits except the internal reference are powered down.
The CODEC automatically enters the power save mode when the FST or BCLK signal is set to digital
“1” or digital “0”;
Upon power up with FST and BCLK signals present, it will take 2 to 10 milliseconds for the internal
PLL to lock. In addition to the PLL lock-in time, the analog outputs will be set to the internal signal
ground for 1 millisecond. This will avoid power up glitches at the outputs. The digital open drain
outputs will remain at high impedance during this power up delay.
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Publication Release Date: April 2005
Revision A10