W631GU6KB-12-TR Datasheet, PDF (7/160 Pages) Winbond – 8M  8 BANKS  16 BIT DDR3L SDRAM

W631GU6KB
4. KEY PARAMETERS
Speed Bin
DDR3L-1866 DDR3L-1600 DDR3L-1333
CL-nRCD-nRP
Part Number Extension
13-13-13
-11
11-11-11
-12/12I
9-9-9
Unit
-15/15I
Parameter
Sym. Min. Max. Min. Max. Min. Max.
Maximum operating frequency using maximum
allowed settings for Sup_CL and Sup_CWL
Internal read command to first data
fCKMAX
tAA
ACT to internal read or write delay time
tRCD
PRE command period
tRP
ACT to ACT or REF command period
ACT to PRE command period
tRC
tRAS

13.91
13.91
13.91
47.91
34
933

800

667 MHz
13.75
13.5
20 _{(13.125) *5} 20 _{(13.125) *5} 20
nS
13.75
13.5

(13.125) *⁵

(13.125) *⁵

nS
13.75
13.5

(13.125) *⁵

(13.125) *⁵

nS
48.75
49.5

(48.125) *⁵

(49.125) *⁵

nS
9 * tREFI
35
9 * tREFI
36
9 * tREFI nS
CL = 6
CWL = 5
CL = 7
CWL = 6
CL = 8
CWL = 6
CL = 9
CWL = 7
CL = 10
CWL = 7
CL = 11
CWL = 8
CL = 13
CWL = 9
Supported CL Settings
Supported CWL Settings
Average periodic
refresh Interval
-40°C ≤ TCASE ≤ 85°C
0°C ≤ TCASE ≤ 85°C
85°C < TCASE ≤ 95°C
Operating One Bank Active-Precharge Current
Operating One Bank Active-Read-Precharge
Current
Operating Burst Read Current
Operating Burst Write Current
Burst Refresh Current
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
Sup_CL
Sup_CWL
tREFI
IDD0
IDD1
IDD4R
IDD4W
IDD5B
2.5
3.3
2.5
3.3
Reserved
1.875
< 2.5
1.875
< 2.5
1.875
< 2.5
Reserved
1.5
< 1.875
1.5
< 1.875
1.5
< 1.875
Reserved
1.25
< 1.5
1.07
< 1.25
Reserved
6, 8, 10, 13
6, (7), 8, (9), 10, 11
5, 6, 7, 9

 *²

7.8 *¹

3.9 *⁴
5, 6, 7, 8

7.8 *^{2, 3}

7.8 *¹

3.9 *⁴

130

115

165

145

330

280

260

220

185

170
2.5
3.3
nS
1.875
< 2.5
nS
1.875
< 2.5
nS
1.5
< 1.875 nS
1.5
< .875 nS
Reserved
nS
Reserved
nS
6, (7), 8, 9, 10
nCK
5, 6, 7
nCK

7.8 *^{2, 3} μS

7.8 *¹ μS

3.9 *⁴ μS

105
mA

130
mA

240
mA

190
mA

160
mA
Self-Refresh Current, T_OPER = 0 ~ 85°C
Operating Bank Interleave Current
IDD6
IDD7

14


430

14

400

14
mA
380
mA
Notes: (Field value contents in blue font or parentheses are optional AC parameter and CL setting)
1. All speed grades support 0°C ≤ TCASE ≤ 85°C with full JEDEC AC and DC specifications.
2. For -11, -12 and -15 speed grades, -40°C ≤ TCASE < 0°C is not available.
3. 12I and 15I speed grades support -40°C ≤ TCASE ≤ 85°C with full JEDEC AC and DC specifications.
4. For all speed grade parts, TCASE is able to extend to 95°C with doubling Auto Refresh commands in frequency to a 32 mS
period ( tREFI = 3.9 µS), it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range
capability (MR2 A6 = 0_b and MR2 A7 = 1_b) or enable the Auto Self-Refresh mode (ASR) (MR2 A6 = 1_b, MR2 A7 is don't care).
5. For devices supporting optional down binning to CL=7 and CL=9, tAA/tRCD/tRP min must be 13.125 nS or lower. SPD settings must
be programmed to match. For example, DDR3L-1333 (9-9-9) devices supporting down binning to DDR3L-1066 (7-7-7) should
program 13.125 nS in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3L-1600 (11-11-11) devices
supporting down binning to DDR3L-1333 (9-9-9) or DDR3L-1066 (7-7-7) should program 13.125 nS in SPD bytes for tAAmin
(Byte16), tRCDmin (Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125 nS, tRCmin (Byte 21, 23) also
should be programmed accodingly. For example, 49.125nS (tRASmin + tRPmin = 36 nS + 13.125 nS) for DDR3L-1333 (9-9-9) and
48.125 nS (tRASmin + tRPmin = 35 nS + 13.125 nS) for DDR3L-1600 (11-11-11).
Publication Release Date: Jan. 20, 2015
Revision: A07
-7-