W631GU6KB-12-TR Datasheet, PDF (17/160 Pages) Winbond – 8M  8 BANKS  16 BIT DDR3L SDRAM

W631GU6KB
8.3.1 Mode Register MR0
The mode register MR0 stores the data for controlling various operating modes of DDR3L SDRAM. It
controls burst length, read burst type, CAS latency, test mode, DLL reset, WR and DLL control for
precharge Power Down, which include various vendor specific options to make DDR3L SDRAM useful
for various applications. The mode register is written by asserting low on CS#, RAS#, CAS#, WE#,
BA0, BA1 and BA2, while controlling the states of address pins according to the Figure 5 below.
BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Field
0^*1
0
0 PPD
WR
DLL TM
CL
RBT CL
BL
Mode Register 0
BA1
0
0
1
1
A8 DLL Reset
0
No
1
Yes
A7
Mode
0
Normal
BA0
MRS mode
1
Test
0
MR0
1
MR1
Write recovery for Auto precharge
0
MR2
A11 A10 A9 WR(cycles)
1
MR3
000
16^*2
001
5^*2
A12 DLL Control for Precharge PD 0 1 0
6^*2
0
Slow exit (DLL off)
011
7^*2
1
Fast exit (DLL on)
100
8^*2
101
10^*2
110
12^*2
111
14^*2
A3 Read Burst Type
0 Nibble Sequential
1
Interleave
CAS Latency
A6 A5 A4 A2
0000
0010
0100
0110
1000
1010
1100
1110
0001
0011
0101
0111
1001
1011
1101
1111
Burst Length
A1 A0
BL
00
8 (Fixed)
0 1 BC4 or 8 (on the fly)
10
BC4 (Fixed)
11
Reserved
Latency
Reserved
Reserved
6
7
8
9
10
11
Reserved
13
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Notes:
1. BA2 is reserved for future use and must be programmed to “0” during MRS.
2. WR (write recovery for Auto precharge)min in clock cycles is calculated by dividing tWR (in nS) by tCK (in nS) and rounding
up to the next integer: WRmin[cycles] = Roundup(tWR[nS] / tCK(avg)[nS]). The WR value in the mode register must be
programmed to be equal or larger than WRmin. The programmed WR value is used with tRP to determine tDAL.
3. The table only shows the encodings for a given Cas Latency. For actual supported CAS Latency, please refer to “Speed
Bins” tables for each frequency.
4. The table only shows the encodings for Write Recovery. For actual Write recovery timing, please refer to AC timing table.
Figure 5 – MR0 Definition
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Publication Release Date: Jan. 20, 2015
Revision: A07