W631GU6KB-12-TR Datasheet, PDF (155/160 Pages) Winbond – 8M  8 BANKS  16 BIT DDR3L SDRAM

W631GU6KB
10.16.5 Data Setup, Hold and Slew Rate Derating
For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the
data sheet tDS(base) and tDH(base) value (see Table 53) to the ΔtDS and ΔtDH (see Table 54 and Table
55) derating value respectively. Example: tDS (total setup time) = tDS(base) + ΔtDS.
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing
of VREF(DC) and the first crossing of VIH(AC)min. Setup (tDS) nominal slew rate for a falling signal is
defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)max
(see Figure 107). If the actual signal is always earlier than the nominal slew rate line between shaded
‘VREF(DC) to AC region’, use nominal slew rate for derating value. If the actual signal is later than the
nominal slew rate line anywhere between shaded ‘VREF(DC) to AC region’, the slew rate of a tangent
line to the actual signal from the AC level to DC level is used for derating value (see Figure 109).
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
VIL(DC)max and the first crossing of VREF(DC). Hold (tDH) nominal slew rate for a falling signal is
defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC)
(see Figure 108). If the actual signal is always later than the nominal slew rate line between shaded
‘DC level to VREF(DC) region’, use nominal slew rate for derating value. If the actual signal is earlier
than the nominal slew rate line anywhere between shaded ‘DC to VREF(DC) region’, the slew rate of a
tangent line to the actual signal from the DC level to VREF(DC) level is used for derating value (see
Figure 110).
For a valid transition the input signal has to remain above/below VIH/IL(AC) for some time tVAC (see
Table 56).
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not
have reached VIH/IL(AC) at the time of the rising clock transition) a valid input signal is still required to
complete the transition and reach VIH/IL(AC).
For slew rates in between the values listed in the tables the derating values may obtained by linear
interpolation.
These values are typically not subject to production test. They are verified by design and
characterization.
Table 53 – Data Setup and Hold Base-Values
Symbol
Reference
DDR3L-1333 DDR3L-1600
tDS(base) AC135 VIH/L(AC) : SR=1 V/nS
45
25
tDS(base) AC130 VIH/L(AC) : SR=2 V/nS


tDH(base) DC90 VIH/L(DC) : SR=1 V/nS
75
55
tDH(base) DC90 VIH/L(DC) : SR=2 V/nS


Notes:
1. (AC/DC referenced for 1V/nS DQ-slew rate and 2 V/nS DQS slew rate)
2. (AC/DC referenced for 2V/nS DQ-slew rate and 4 V/nS DQS slew rate).
DDR3L-1866

70

70
Unit Note
pS
1
pS
2
pS
1
pS
2
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Publication Release Date: Jan. 20, 2015
Revision: A07