W25Q16DVSSIG Datasheet, PDF (67/81 Pages) Winbond – 3V 16M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI

W25Q16DV
8.7 AC Electrical Characteristics (cont’d)
DESCRIPTION
SYMBOL
ALT
MIN
SPEC
TYP
MAX
UNIT
/HOLD Active Hold Time relative to CLK
tCHHH
3
ns
/HOLD Not Active Setup Time relative to CLK
tHHCH
3
ns
/HOLD Not Active Hold Time relative to CLK
/HOLD to Output Low-Z
/HOLD to Output High-Z
Write Protect Setup Time Before /CS Low
Write Protect Hold Time After /CS High
/CS High to Power-down Mode
/CS High to Standby Mode without Electronic
Signature Read
/CS High to Standby Mode with Electronic Signature
Read
/CS High to next Instruction after Suspend
tCHHL
tHHQX⁽²⁾
tHLQZ⁽²⁾
tWHSL⁽³⁾
tSHWL⁽³⁾
tDP⁽²⁾
tRES1⁽²⁾
tRES2⁽²⁾
tSUS⁽²⁾
3
tLZ
tHZ
20
100
ns
7
ns
12
ns
ns
ns
3
µs
3
µs
1.8
µs
20
µs
Write Status Register Time
tW
Byte Program Time (First Byte) ⁽⁴⁾
t_BP1
Additional Byte Program Time (After First Byte) ⁽⁴⁾
t_BP2
Page Program Time
tPP
Sector Erase Time (4KB)
tSE
10
15
ms
20
50
µs
2.5
10
µs
0.7
3
ms
60 200/400⁽⁵⁾ ms
Block Erase Time (32KB)
Block Erase Time (64KB)
Chip Erase Time
tBE₁
150
800
ms
tBE₂
180
1,000
ms
tCE
3
10
s
Notes:
1.
2.
3.
4.
5.
Clock high + Clock low must be less than or equal to 1/fC.
Value guaranteed by design and/or characterization, not 100% tested in production.
Only applicable as a constraint for a Write Status Register instruction when SRP[1:0]=(0,1).
For multiple bytes after first byte within a page, t_BPN = t_{BP1 +} t_{BP2 * N} (typical) and t_BPN = t_{BP1 +} t_{BP2 * N} (max), where N =
number of bytes programmed.
Max Value tSE with <50K cycles is 200ms and >50K & <100K cycles is 400ms.
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Publication Release Date: October 29, 2012
Revision D