W83193R-02 Datasheet, PDF (6/18 Pages) Winbond – 83.3 MHZ 3-DIMM CLOCK

Preliminary W83193R-02/-04/-04A
The W83193R-02/-04/-04A may be disabled in the low state according to the following table in order
to reduce power consumption. All clocks are stopped in the low state, but maintain a valid high period
on transitions from running to stop. The CPU and PCI clocks transform between running and stop by
waiting for one positive edge on PCICLK_F followed by negative edge on the clock of interest, after
which high levels of the output are either enabled or disabled.
CPU_STOP#
0
0
1
1
PCI_STOP#
0
1
0
1
CPU
Low
Low
Running
Running
PCI
Low
Running
Low
Running
OTHER CLKs
Running
Running
Running
Running
XTAL & VCOs
Running
Running
Running
Running
8.2 2-Wire I²C Control Interface
The clock generator is a slave I²C component which can be read back the data stored in the latches
for verification. All proceeding bytes must be sent to change one of the control bytes. The 2-wire
control interface allows each clock output individually enabled or disabled. On power up, the
W83193R-02/-04/-04A initializes with default register settings, and then it's optional to use the 2-wire
control interface.
The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high
during normal data transfer. There are only two exceptions. One is a high-to-low transition on SDATA
while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a low-to-
high transition on SDATA while SDCLK is high used to indicate the end of a data transfer cycle. Data
is always sent as complete 8-bit bytes followed by an acknowledge generated.
Byte writing starts with a start condition followed by 7-bit slave address and a write command bit
[1101 0010], command code checking [0000 0000], and byte count checking. After successful
reception of each byte, an acknowledge (low) on the SDATA wire will be generated by the clock chip.
Controller can start to write to internal I²C registers after the string of data. The sequence order is as
follows:
Bytes sequence order for I²C controller:
Clock Address
A(6:0) & R/W
Ack
8 bits dummy
Command code
Ack
8 bits dummy
Byte count
Ack
Byte0,1,2...
until Stop
Set R/W to 1 when read back, the data sequence is as follows:
Clock Address
A(6:0) & R/W
Ack
Byte 0
Ack
Byte 1
Ack
Byte2, 3, 4...
until Stop
8.3 Serial Control Registers
The pin column lists the affected pin number and the @PowerUp column gives the state at true power
up. Registers are set to the values shown only on true power up. "Command Code" byte and "Byte
Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in
these two bytes are considered "don't care", they must be sent and will be acknowledge. After that,
the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and
acknowledged.
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