W83193R-02 Datasheet, PDF (13/18 Pages) Winbond – 83.3 MHZ 3-DIMM CLOCK

Preliminary W83193R-02/-04/-04A
9.4.5 Type 5 Buffer for PCICLK (0:5, F)
PARAMETER
Pull-up Current Min.
Pull-up Current Max.
Pull-down Current Min.
Pull-down Current Max.
Rise/Fall Time Min.
Between 0.8V and 2.0V
Rise/Fall Time Max.
Between 0.8V and 2.0V
SYMBOL
IOH (min.)
IOH (max.)
IOL (min.)
IOL (max.)
TRF (min.)
MIN.
-33
30
0.5
TRF (max.)
TYP.
MAX.
-33
38
UNITS
mA
mA
mA
mA
nS
TEST CONDITIONS
Vout = 1.0V
Vout = 3.135V
Vout = 1.95V
Vout = 0.4V
15 pF Load
2.0 nS 30 pF Load
10.0 POWER MANAGEMENT TIMING
10.1 CPU_STOP# Timing Diagram (synchronous)
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK_F
CPU_STOP#
CPUCLK[0:3]
SDRAM
1
2
1
2
For synchronous Chipset, CPU_STOP# pin is a synchronous "active low" input pin used to stop the
CPU clocks for low power operation. This pin is asserted synchronously by the external control logic
at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run while the
CPU clocks are stopped. The CPU clocks will always be stopped in a low state and resume output
with full pulse width. In this case, CPU "clocks on latency" is less than 2 CPU clocks and "clocks off
latency" is less then 2 CPU clocks.
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Publication Release Date: April 1999
Revision A1