W39V080FA Datasheet, PDF (6/35 Pages) Winbond – 1M × 8 CMOS FLASH MEMORY WITH FWH INTERFACE

W39V080FA
6.6 Sector Erase Command
Sector erase is a six bus cycles operation. There are two "unlock" write cycles, followed by writing the
"set-up" command. Two more "unlock" write cycles then follows by the Sector erase command. The
Sector address (any address location within the desired Sector) is latched on the rising edge of R/#C in
programmer mode, while the command (30H) is latched on the rising edge of #WE.
Sector erase does not require the user to program the device prior to erase. When erasing a Sector,
the remaining unselected sectors are not affected. The system is not required to provide any controls or
timings during these operations.
The automatic Sector erase begins after the erase command is completed, right from the rising edge of
the #WE pulse for the last Sector erase command pulse and terminates when the data on DQ7, Data
Polling, is "1" at which time the device returns to the read mode. Data Polling must be performed at an
address within any of the sectors being erased.
Refer to the Erase Command flow Chart using typical command strings and bus operations.
6.7 Program Operation
The W39V080FA is programmed on a byte-by-byte basis. Program operation can only change logical
data "1" to logical data "0." The erase operation, which changed entire data in main memory and/or
boot block from "0" to "1", is needed before programming.
The program operation is initiated by a 4-byte command cycle (see Command Codes for Byte
Programming). The device will internally enter the program operation immediately after the
byte-program command is entered. The internal program timer will automatically time-out (9μS
typ.-TBP) once it is completed and then return to normal read mode. Data polling and/or Toggle Bits can
be used to detect end of program cycle.
6.8 Dual BIOS
The W39V080FA provides a solution for Dual-BIOS application. In FWH mode, when D/#F is low, the
device functions as a full-chip partition of 8M-bit which address ranges from FFFFFh to 00000h with
A[19:0]. If D/#F is driven high, the device functions as a dual-block partition that each block consists of
4M-bit. For dual-block partition, there is only one 4M-bit block, either upper or lower, can be
accessed. The U/#L pin selects either upper or lower 4M-bit block and its address ranges from
7FFFFh to 00000h with A[19:0]. When U/#L is low, the lower 4M-bit block will be selected; while, U/#L
is high, the upper 4M-bit block will be selected.
6.9 Hardware Data Protection
The integrity of the data stored in the W39V080FA is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle.
(2) VDD Power Up/Down Detection: The programming and read operation are inhibited when VDD is
less than 2.0V typical.
(3) Write Inhibit Mode: Forcing #OE low or #WE high will inhibit the write operation. This prevents
inadvertent writes during power-up or power-down periods.
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