W39V080FA Datasheet, PDF (4/35 Pages) Winbond – 1M × 8 CMOS FLASH MEMORY WITH FWH INTERFACE

W39V080FA
3. PIN CONFIGURATIONS
NC
1
NC
2
NC
VSS
IC
3
4
5
A10(FGPI4)
6
R/#C(CLK)
7
V DD
8
Vpp
9
#RESET
10
A9(FGPI3)
11
A8(FGPI2)
12
A7(FGPI1)
13
A6(FGPI0)
14
A5(#WP)
15
A4(#TBL)
16
A7(FGPI1)
A6(FGPI0)
A5(#WP)
A4(#TBL)
A3(ID3)
A2(ID2)
A1(ID1)
A0(ID0)
DQ0(FWH0)
32L STSOP
32 #OE(#INIT)
31
30
29
28
27
26
25
24
23
#WE(FWH4)
RY/#BY(RSV)
DQ7(U/#L)
DQ6(D/#F)
DQ5(RSV)
DQ4(RSV)
DQ3(FWH3)
VSS
DQ2(FWH2)
22 DQ1(FWH1)
21
DQ0(FWH0)
20 A0(ID0)
19
A1(ID1)
18
A2(ID2)
17
A3(ID3)
A
AA
R1
89
/0
^
F
G
P
I
2
v
^
F
G
P
I
3
v
#
R
E
S
E
T
VV
PD
PD
#
C
^
C
L
K
v
^
F
G
P
I
4
v
4 3 2 1 32 31 30
5
29
6
28
7
27
8
26
9 _{32L PLCC} 25
10
24
11
23
12
22
13
21
14 15 16 17 18 19 20
IC
VSS
NC
NC
VDD
#OE(#INIT)
#WE(FWH4)
RY/#BY(RSV)
DQ7(U/#L)
DD
QQ
12
^^
FF
WW
HH
12
vv
V DD
S QQ
S34
^^
FR
WS
HV
3v
v
DD
QQ
56
^^
RD
S/
V#
vF
v
NC
1
IC
2
NC 3
NC 4
NC ₅
NC ₆
A10(FGPI4) 7
NC
CLK
8
9
VDD ₁₀
Vpp
11
#RESET 12
NC
13
NC 14
A9(FGPI3) 15
A8(FGPI2) 16
A7(FGPI1) 17
A6(FGPI0) ₁₈
A5(#WP) 19
A4(#TBL) 20
40L TSOP
40
VSS
39
VDD
38 #WE(FWH4)
37 #OE(#INIT)
36 RY/#BY(RSV)
35
DQ7(U/#L)
34
DQ6(D/#F)
33
DQ5(RSV)
32
DQ4(RSV)
31
VDD
30
VSS
29
VSS
28 DQ3(FWH3)
27 DQ2(FWH2)
26 DQ1(FWH1)
25 DQ0(FWH0)
24 A0(ID0)
23 A1(ID1)
22 A2(ID2)
21 A3(ID3)
4. BLOCK DIAGRAM
#WP
#TBL
CLK
FWH[3:0]
FWH4
FWH
Interface
IC
#INIT
#RESET
64K BYTES BLOCK 15
64K BYTES BLOCK 14
64K BYTES BLOCK 13
0FFFFF
0F0000
0EFFFF
0E0000
0DFFFF
0D0000
0CFFFF
R/#C
A[10:0]
DQ[7:0]
#OE
#WE
RY/#BY
Program-
mer
Interface
64K BYTES BLOCK 2
64K BYTES BLOCK 1
64K BYTES BLOCK 0
030000
02FFFF
020000
01FFFF
010000
00FFFF
000000
5. PIN DESCRIPTION
SYM.
IC
#RESET
#INIT
#TBL
#WP
CLK
FGPI[4:0]
ID[3:0]
FWH[3:0]
FWH4
D/#F
U/#L
R/#C
A[10:0]
DQ[7:0]
#OE
#WE
RY/#BY
VDD
VSS
VPP
RSV
NC
INTERFACE
PGM FWH
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
**
*
*
*
*
*
*
*
*
PIN NAME
Interface Mode Selection
Reset
Initialize
Top Boot Block Lock
Write Protect
CLK Input
General Purpose Inputs
Identification Inputs
Pull Down with Internal Resistors
Address/Data Inputs
FWH Cycle Initial
Dual Bios/Full Chip
Pull Down with Internal Resistors
Upper 4M/Lower 4M
Pull Down with Internal Resistors
Row/Column Select
Address Inputs
Data Inputs/Outputs
Output Enable
Write Enable
Ready/ Busy
Power Supply
Ground
Accelerate Program Power Supply
Reserved Pins
No Connection
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