W39V080FA Datasheet, PDF (23/35 Pages) Winbond – 1M × 8 CMOS FLASH MEMORY WITH FWH INTERFACE

W39V080FA
Timing Waveforms for Programmer Interface Mode, continued
9.3 Program Cycle Timing Diagram
A[10:0]
(Internal A[19:0])
DQ[7:0]
R/#C
Byte Program Cycle
5555
AA
2AAA
55
5555
Programmed Address
A0
Data-In
#OE
#WE
RY/#BY
TWPH
TWP
Byte 0
Byte 1
TBP
Byte 2
Byte 3
Internal Write Start
TBUSY
Note: The internal address A[19:0] are converted from external Column/Row address.
Column/Row Address are mapped to the Low/High order internal address.
i.e. Column Address A[10:0] are mapped to the internal A[10:0],
Row Address A[8:0] are mapped to the internal A[19:11].
9.4 #DATA Polling Timing Diagram
A[10:0]
(Internal A[19:0])
An
R/ #C
#WE
#OE
DQ7
X
An
TOEP
RY/#BY
TBUSY
X
TBP
An
An
X
X
- 23 -
Publication Release Date: Dec. 13, 2005
Revision A5