W39V080FA Datasheet, PDF (21/35 Pages) Winbond – 1M × 8 CMOS FLASH MEMORY WITH FWH INTERFACE

W39V080FA
Programmer Interface Mode AC Characteristics, continued
8.3 Read Cycle Timing Parameters
(VDD = 3.3V ± 0.3V, VSS = 0V, TA = 0 to 70° C)
PARAMETER
SYMBOL
Read Cycle Time
Row / Column Address Set Up Time
Row / Column Address Hold Time
Address Access Time
Output Enable Access Time
#OE Low to Active Output
#OE High to High-Z Output
Output Hold from Address Change
TRC
TAS
TAH
TAA
TOE
TOLZ
TOHZ
TOH
W39V080FA
MIN.
MAX.
350
-
50
-
50
-
-
200
-
75
0
-
-
35
0
-
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
8.4 Write Cycle Timing Parameters
PARAMETER
SYMBOL MIN.
TYP.
MAX.
UNIT
Reset Time
TRST
1
-
-
μS
Address Setup Time
TAS
50
-
-
nS
Address Hold Time
TAH
50
-
-
nS
R/#C to Write Enable High Time
TCWH
50
-
-
nS
#WE Pulse Width
TWP
100
-
-
nS
#WE High Width
TWPH
100
-
-
nS
Data Setup Time
TDS
50
-
-
nS
Data Hold Time
TDH
50
-
-
nS
#OE Hold Time
TOEH
0
-
-
nS
Byte programming Time
TBP
-
9
250
μS
Sector Erase Cycle Time (Note (c))
TPEC
-
0.9
6
S
Program/Erase Valid to RY/#BY Delay
TBUSY
90
-
-
nS
Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is input high and
(b) low level signal's reference level is input low. Ref. to the AC testing condition.
(c) Exclude 00H pre-program prior to erasure. (In the pre-programming step of the embedded erase algorithm, all bytes are
programmed to 00H before erasure
8.5 Data Polling and Toggle Bit Timing Parameters
PARAMETER
#OE to Data Polling Output Delay
#OE to Toggle Bit Output Delay
Toggle or Polling interval
SYMBOL
TOEP
TOET
---
W39V080FA
MIN.
MAX.
-
40
-
40
50
-
UNIT
nS
nS
mS
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Publication Release Date: Dec. 13, 2005
Revision A5