W9825G6JH Datasheet, PDF (5/42 Pages) Winbond – 4 M  4 BANKS  16 BITS SDRAM

W9825G6JH
5. PIN DESCRIPTION
PIN NUMBER PIN NAME FUNCTION
DESCRIPTION
2326, 22,
2936
A0A12
Address
Multiplexed pins for row and column address.
Row address: A0A12. Column address: A0A8.
20, 21
BS0, BS1
Bank Select
Select bank to activate during row address latch time, or
bank to read/write during address latch time.
2, 4, 5, 7, 8, 10,
11, 13, 42, 44,
45, 47, 48, 50,
DQ0DQ15
51, 53
Data
Input/Output
Multiplexed pins for data output and input.
Disable or enable the command decoder. When
19
CS
Chip Select command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising edge of
18
RAS
Row Address
Strobe ^{the clock, RAS , CAS and WE define the operation}
to be executed.
Column
17
CAS
Address _{Referred to RAS}
Strobe
16
15, 39
38
37
1, 14, 27
28, 41, 54
3, 9, 43, 49
6, 12, 46, 52
40
WE
LDQM,
UDQM
CLK
CKE
VDD
VSS
VDDQ
VSSQ
NC
Write Enable _{Referred to RAS}
Input/Output
Mask
The output buffer is placed at Hi-Z(with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write operation
with zero latency.
Clock Inputs
System clock used to sample inputs on the rising edge
of clock.
CKE controls the clock activation and deactivation.
Clock Enable When CKE is low, Power Down mode, Suspend mode,
or Self Refresh mode is entered.
Power (+3.3V) Power for input buffers and logic circuit inside DRAM.
Ground Ground for input buffers and logic circuit inside DRAM.
Power (+3.3V) Separated power from VDD, to improve DQ noise
for I/O Buffer immunity.
Ground Separated ground from VSS, to improve DQ noise
for I/O Buffer immunity.
No Connection No connection.
Publication Release Date: Nov. 29, 2011
-5-
Revision A04