W9825G6JH Datasheet, PDF (36/42 Pages) Winbond – 4 M  4 BANKS  16 BITS SDRAM

W9825G6JH
11.16 Auto-precharge Timing (Write Cycle)
0
1
2
3
4
5
6
7
8
9
CLK
(1) CAS Latency = 2
(a) burst length = 1
Command
Write
tWR
DQ
D0
(b) burst length = 2
Command
Write
DQ
D0
D1
(c) burst length = 4
Command
Write
DQ
D0
D1
(d) burst length = 8
Command
Write
DQ
D0
D1
(2) CAS Latency = 3
(a) burst length = 1
Command
Write
tWR
DQ
D0
(b) burst length = 2
Command
Write
DQ
D0
D1
(c) burst length = 4
Command
Write
DQ
D0
D1
(d) burst length = 8
Command
Write
DQ
D0
D1
AP
tWR
D2
D2
AP
tWR
D2
D2
Act
tRP
AP
Act
tRP
AP
tWR
D3
D3
D4
D5
Act
tRP
AP
tRP
AP
tWR
D3
D3
D4
D5
Act
tRP
D6
D7
Act
tRP
D6
D7
AP
tWR
Act
AP
tWR
10 11 12
Act
tRP
Act
tRP
Note )
Write
represents the Write with Auto precharge command.
AP
represents the start of internal precharing.
Act
represents the Bank Activ e command.
When the /auto precharge command is asserted,the period f rom Bank Activ ate
command to the start of intermal precgarging must be at least tRAS (min).
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Publication Release Date: Nov. 29, 2011
Revision A04