W9812G6JH Datasheet, PDF (5/42 Pages) Winbond – 2M × 4 BANKS × 16 BITS SDRAM

W9812G6JH
5. PIN DESCRIPTION
PIN NUMBER PIN NAME FUNCTION
DESCRIPTION
23 − 26, 22,
29 − 35
A0 − A11
Address
Multiplexed pins for row and column address.
Row address: A0 − A11. Column address: A0 − A8.
20, 21
BS0, BS1
Bank Select
Select bank to activate during row address latch time,
or bank to read/write during address latch time.
2, 4, 5, 7, 8,
10, 11, 13, 42,
44, 45, 47, 48,
50, 51, 53
DQ0 −
DQ15
Data Input/
Output
Multiplexed pins for data output and input.
Disable or enable the command decoder. When
19
CS
Chip Select command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising edge of
18
RAS
Row Address
Strobe
the clock, RAS , CAS and WE define the
operation to be executed.
17
CAS
Column Address
Strobe
Referred to
RAS
16
WE
Write Enable _{Referred to RAS}
39, 15
UDQM/
LDQM
Input/Output
Mask
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
38
CLK
Clock Inputs
System clock used to sample inputs on the rising edge
of clock.
CKE controls the clock activation and deactivation.
37
CKE
Clock Enable When CKE is low, Power Down mode, Suspend mode
or Self Refresh mode is entered.
1, 14, 27
VDD
Power (+3.3V) Power for input buffers and logic circuit inside DRAM.
28, 41, 54
VSS
Ground
Ground for input buffers and logic circuit inside DRAM.
3, 9, 43, 49
VDDQ
Power (+3.3V) Separated power from VDD, used for output buffers to
for I/O Buffer improve noise.
6, 12, 46, 52
VSSQ
Ground for I/O Separated ground from VSS, used for output buffers to
Buffer
improve noise.
36, 40
NC
No Connection No connection
Publication Release Date: Sep. 08, 2010
-5-
Revision A04