W9812G6JH Datasheet, PDF (15/42 Pages) Winbond – 2M × 4 BANKS × 16 BITS SDRAM

W9812G6JH
9.5 AC Characteristics and Operating Condition
(VDD = 3.3V ± 0.3V, TA = 0 to 70°C for -5/-6/-75, TA= -40 to 85°C for -6I/-6A) (Notes: 5, 6)
PARAMETER
Ref/Active to Ref/Active Command
Period
Active to precharge Command Period
Active to Read/Write Command Delay
Time
Read/Write(a) to Read/Write(b)
Command Period
Precharge to Active Command Period
Active(a) to Active(b) Command Period
Write Recovery Time
CL* = 2
CL* = 3
CLK Cycle Time
CL* = 2
CL* = 3
CLK High Level width
CLK Low Level width
Access Time from CLK
CL* = 2
CL* = 3
Output Data Hold Time
Output Data High
Impedance Time
CL* = 2
CL* = 3
Output Data Low Impedance Time
Power Down Mode Entry Time
Transition Time of CLK (Rise and Fall)
Data-in Set-up Time
Data-in Hold Time
Address Set-up Time
Address Hold Time
CKE Set-up Time
CKE Hold Time
Command Set-up Time
Command Hold Time
Refresh Time
Mode register Set Cycle Time
Exit self refresh to ACTIVE command
*CL = CAS Latency
-5
SYM.
MIN. MAX.
-6/-6I/-6A
MIN. MAX.
-75
MIN. MAX.
UNIT NOTES
t_RC 55
60
65
t_RAS 40 100000 42 100000 45 100000 nS
t_RCD 15
15
20
t_CCD 1
1
1
t_CK
t_RP 15
15
20
nS
t_RRD 10
12
15
2
2
2
t_WR
2
2
2
t_CK
10 1000 7.5 1000 10 1000
t_CK
5
1000
6
1000 7.5 1000
t_CH
2
2
2.5
8
t_CL
2
2
2.5
8
6
6
6
t_AC
4.5
5
5.4
9
t_OH
3
3
3
9
6
6
6
7
t_HZ
4.5
5
5.4
t_LZ
0
0
0
9
t_SB
0
5
0
6
0
7.5
nS
t_T
1
1
1
t_DS 1.5
1.5
1.5
8
t_DH 0.8
0.8
0.8
8
t_AS 1.5
1.5
1.5
8
t_AH 0.8
0.8
0.8
8
t_CKS 1.5
1.5
1.5
8
t_CKH 0.8
0.8
0.8
8
t_CMS 1.5
1.5
1.5
8
t_CMH 0.8
0.8
0.8
8
t_REF
64
64
64 mS
t_RSC 2
2
2
t_CK
t_XSR 70
72
75
nS
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Publication Release Date: Sep. 08, 2010
Revision A04