W9864G6JH_13 Datasheet, PDF (40/43 Pages) Winbond – 1M x 4 BANKS x 16 BITS SDRAM

W9864G6JH
11.21 CKE/DQM Input Timing (Write Cycle)
CLK cycle No.
1
2
External
CLK
Internal
CKE
DQM
DQ
D1
D2
3
4
5
6
7
D3
D5
D6
DQM MASK
( 1)
CKE MASK
CLK cycle No.
1
2
External
CLK
Internal
CKE
DQM
DQ
D1
D2
CLK cycle No.
1
2
External
CLK
Internal
CKE
DQM
DQ
D1
D2
3
4
5
6
7
D3
D5
D6
DQM MASK
( 2)
CKE MASK
3
4
5
6
7
D3
D4
CKE MASK
( 3)
D5
D6
- 40 -
Publication Release Date: Jun. 25, 2013
Revision A04