W9864G6JH_13 Datasheet, PDF (38/43 Pages) Winbond – 1M x 4 BANKS x 16 BITS SDRAM

W9864G6JH
11.17 Timing Chart of Read to Write Cycle
In the case of Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10 11
(1) CAS Latency= 2
( a ) Command
Read Write
DQM
DQ
D0 D1 D2 D3
( b) Command
DQM
DQ
Read
Write
D0 D1 D2 D3
(2) CAS Latency= 3
( a ) Command
DQM
DQ
( b) Command
DQM
DQ
Read Write
D0 D1 D2 D3
Read
Write
D0 D1 D2 D3
Note: The Output data must be masked by DQM to avoid I/O conflict
11.18 Timing Chart of Write to Read Cycle
In the c as e of B urs t Length=4
01
2
3
(1) CAS Latency= 2
( a ) Command
DQM
Write Read
DQ
D0
4
5
6
7
8
Q0 Q1 Q2 Q3
9 10 11
( b) Command
DQM
DQ
(2) CAS Latency= 3
( a ) Command
DQM
W rit e
Read
D0 D1
Write Read
Q0 Q1 Q2 Q3
DQ
D0
Q0 Q1 Q2 Q3
( b) Command
DQM
DQ
W rit e
Read
D0 D1
Q0 Q1 Q2 Q3
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Publication Release Date: Jun. 25, 2013
Revision A04