W9864G6JH_13 Datasheet, PDF (37/43 Pages) Winbond – 1M x 4 BANKS x 16 BITS SDRAM

W9864G6JH
11.16 Auto-precharge Timing (Read Cycle)
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(1) CAS Latency=2
( a ) burst length = 1
Command _{Read AP}
Act
tRP
DQ
Q0
( b ) burst length = 2
Command _Read
DQ
AP
Act
tRP
Q0 Q1
( c ) burst length = 4
Command _Read
DQ
AP
Act
tRP
Q0 Q1 Q2 Q3
( d ) burst length = 8
Command _Read
DQ
AP
Act
tRP
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
(2) CAS Latency=3
( a ) burst length = 1
Command Read
AP
DQ
Act
tRP
Q0
( b ) burst length = 2
Command Read
DQ
AP
Act
tRP
Q0 Q1
( c ) burst length = 4
Command Read
DQ
AP
Act
tRP
Q0 Q1 Q2 Q3
( d ) burst length = 8
Command Read
DQ
AP
Act
tRP
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Note )
Read
represents the Read with Auto precharge command.
AP
represents the start of internal precharging.
Act
represents the Bank Activate command.
When the Auto precharge command is asserted, the period from Bank Activate command to
the start of internal precgarging must be at leasRt AtS(min).
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Publication Release Date: Jun. 25, 2013
Revision A04