W25X64BV Datasheet, PDF (4/43 Pages) Winbond – 64M-BIT SERIAL FLASH MEMORY WITH 4KB SECTORS AND DUAL OUTPUT SPI

W25X64BV
1. GENERAL DESCRIPTION
The W25X64BV (64M-bit) Serial Flash memory provides a storage solution for systems with limited
space, pins and power. The 25X series offers flexibility and performance well beyond ordinary Serial
Flash devices. They are ideal for code download applications as well as storing voice, text and data.
The devices operate on a single 2.7V to 3.6V power supply with current consumption as low as 4mA
active and 1µA for power-down. All devices are offered in space-saving packages.
The W25X64BV array is organized into 32,768 programmable pages of 256-bytes each. Up to 256
bytes can be programmed at a time using the Page Program instruction. Pages can be erased in
groups of 16 (sector erase), groups of 128 (32KB block erase), groups of 256 (block erase) or the
entire chip (chip erase). The W25X64BV has 2,048 erasable sectors and 128 erasable blocks
respectively. The small 4KB sectors allow for greater flexibility in applications that require data and
parameter storage. (See figure 2.)
The W25X64BV supports the standard Serial Peripheral Interface (SPI), and a high performance dual
output SPI using four pins: Serial Clock, Chip Select, Serial Data I/O and Serial Data Out. SPI clock
frequencies of up to 80MHz are supported allowing equivalent clock rates of 160MHz when using the
Fast Read Dual Output instruction. These transfer rates are comparable to those of 8 and 16-bit
Parallel Flash memories.
A Hold pin, Write Protect pin and programmable write protect, with top or bottom array control
features, provide further control flexibility. Additionally, the device supports JEDEC standard
manufacturer and device identification.
2. FEATURES
 Family of Serial Flash Memories
– W25X64BV: 64M-bit / 8M-byte (8,388,608)
– 256-bytes per programmable page
– Uniform 4K-byte Sectors / 64K-byte Blocks
 SPI with Single or Dual Outputs
– Clock, Chip Select, Data I/O, Data Out
– Optional Hold function for SPI flexibility
 Data Transfer up to 160M-bits / second
– Clock operation to 80MHz
– Fast Read Dual Output instruction
– Auto-increment Read capability
 Software and Hardware Write Protection
– Write-Protect all or portion of memory
– Enable/Disable protection with /WP pin
– Top or bottom array protection
 Flexible Architecture with 4KB sectors
– Sector Erase (4K-bytes)
– Block Erase (32K and 64K-byte)
– Page program up to 256 bytes <1ms
– More than 100,000 erase/write cycles
– More than 20-year retention
 Low Power Consumption, Wide
Temperature Range
– Single 2.7 to 3.6V supply
– 4mA active current, 1µA Power-down (typ)
– -40° to +85°C operating range
 Space Efficient Packaging
– 8-pin SOIC 208-mil
– 8-pad WSON 8x6-mm
– 16-pin SOIC 300-mil
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