W9825G2JB-6I-TR Datasheet, PDF (38/42 Pages) Winbond – 4 M X 4 BANKS X 16 BITS SDRAM

W9825G6JB
11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command)
0
1
2
3
4
5
6
7
8
9
10 11
(1) Read cycle
( a ) CAS latency =2
C ommand Read
BST
DQ
( b )CAS latency = 3
C omma nd
Read
DQ
Q0 Q1 Q2 Q3 Q4
BST
Q0 Q1 Q2 Q3 Q4
(2) Write cycle
C ommand Write
BST
DQ Q0 Q1 Q2 Q3 Q4
Note: BST
represents the Burst stop command
11.20 Timing Chart of Burst Stop Cycle (Precharge Command)
0
1
2
3
4
5
6
7
8
(1) Read cycle
(a) CAS latency =2
Command
DQ
(b) CAS latency =3
Command
DQ
Read
Read
PRCG
Q0
Q1
Q2
Q3
Q4
PRCG
Q0
Q1
Q2
Q3
Q4
9 10 11
(2) Write cycle
Command
Write
PRCG
tWR
DQM
DQ
Q0
Q1
Q2
Q3
Q4
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Publication Release Date: Jul. 17, 2014
Revision: A05