W79E648 Datasheet, PDF (37/80 Pages) Winbond – Fast 8051 Compatible microcontroller with a redesigned Processor

Preliminary W79E648
Table 6. SFR Reset Value, continued
SFR Name
SCON
SBUF
P2
PWMCON2
PWM1
PWM3
PWM5
Reset Value
00000000b
xxxxxxxxb
11111111b
00000000b
00000000b
00000000b
00000000b
SFR Name
B
EIP
PWMCON1
PWM0
PWM2
PWM4
Reset Value
00000000b
xxx00000b
00000000b
00000000b
00000000b
00000000b
The WDCON SFR bits are set/cleared in reset condition depending on the source of the reset.
External reset
Watchdog reset
Power on reset
WDCON
0x0x0xx0b
0x0x01x0b
01000000b
The POR bit WDCON.6 is set only by the power on reset. The WTRF bit WDCON.2 is set when the
Watchdog timer causes a reset. A power on reset will also clear this bit. The EWT bit WDCON.1 is
cleared by power on resets. This disables the Watchdog timer resets. A watchdog or external reset
does not affect the EWT bit.
9. INTERRUPTS
The W79E648 has a two priority level interrupt structure with 11 interrupt sources. Each of the
interrupt sources has an individual priority bit, flag, interrupt vector and enable bit. In addition, the
interrupts can be globally enabled or disabled.
Interrupt Sources
The External Interrupts INT0 and INT1 can be either edge triggered or level triggered, depending on
bits IT0 and IT1. The bits IE0 and IE1 in the TCON register are the flags which are checked to
generate the interrupt. In the edge triggered mode, the INTx inputs are sampled in every machine
cycle. If the sample is high in one cycle and low in the next, then a high to low transition is detected
and the interrupts request flag IEx in TCON is set. The flag bit requests the interrupt. Since the
external interrupts are sampled every machine cycle, they have to be held high or low for at least one
complete machine cycle. The IEx flag is automatically cleared when the service routine is called. If the
level triggered mode is selected, then the requesting source has to hold the pin low till the interrupt is
serviced. The IEx flag will not be cleared by the hardware on entering the service routine. If the
interrupt continues to be held low even after the service routine is completed, then the processor may
acknowledge another interrupt request from the same source.
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Publication Release Date: 05/31/2004
Revision A1