W79E648 Datasheet, PDF (23/80 Pages) Winbond – Fast 8051 Compatible microcontroller with a redesigned Processor

Preliminary W79E648
Interrupt Priority
Bit:
7
-
Mnemonic: IP
6
5
4
3
2
1
0
-
PT2
PS
PT1 PX1 PT0 PX0
Address: B8h
IP.7:
PT2:
PS:
PT1:
PX1:
PT0:
PX0:
This bit is un-implemented and will read high.
This bit defines the Timer 2 interrupt priority. PT2 = 1 sets it to higher priority level.
This bit defines the Serial port 0 interrupt priority. PS = 1 sets it to higher priority level.
This bit defines the Timer 1 interrupt priority. PT1 = 1 sets it to higher priority level.
This bit defines the External interrupt 1 priority. PX1 = 1 sets it to higher priority level.
This bit defines the Timer 0 interrupt priority. PT0 = 1 sets it to higher priority level.
This bit defines the External interrupt 0 priority. PX0 = 1 sets it to higher priority level.
Slave Address Mask Enable
Bit:
7
6
5
4
3
2
1
0
Mnemonic: SADEN
Address: B9h
SADEN: This register enables the Automatic Address Recognition feature of the Serial port 0. When
a bit in the SADEN is set to 1, the same bit location in SADDR will be compared with the
incoming serial data. When SADEN.n is 0, then the bit becomes a "don't care" in the
comparison. This register enables the Automatic Address Recognition feature of the Serial
port 0. When all the bits of SADEN are 0, interrupt will occur for any incoming address.
Power Management Register
Bit:
7
6
5
4
3
2
1
0
-
-
-
-
-
ALE-OFF
-
DME0
Mnemonic: PMR
Address: C4h
ALE0FF: This bit disables the expression of the ALE signal on the device pin during all on-board
program and data memory accesses. External memory accesses will automatically enable
ALE independent of ALEOFF.
0 = ALE expression is enable; 1 = ALE expression is disable
DME0: This bit determines the on-chip MOVX SRAM to be enabled or disabled. Set this bit to 1 will
enable the on-chip 1KB MOVX SRAM.
Status Register
Bit:
7
6
5
4
3
2
1
0
-
HIP
LIP
-
-
-
-
-
Mnemonic: STATUS
Address: C5h
- 23 -
Publication Release Date: 05/31/2004
Revision A1