W79E648 Datasheet, PDF (27/80 Pages) Winbond – Fast 8051 Compatible microcontroller with a redesigned Processor

Preliminary W79E648
RWT:
Reset Watchdog Timer. This bit helps in putting the watchdog timer into a know state. It also
helps in resetting the watchdog timer before a time-out occurs. Failing to set the EWT before
time-out will cause an interrupt, if EWDI (EIE.4) is set, and 512 clocks after that a watchdog
timer reset will be generated if EWT is set. This bit is self-clearing by hardware.
The WDCON SFR is set to a 0x0x0xx0b on an external reset. WTRF is set to a 1 on a Watchdog timer
reset, but to a 0 on power on/down resets. WTRF is not altered by an external reset. POR is set to 1
by a power-on reset. EWT is set to 0 on a Power-on reset and unaffected by other resets.
All the bits in this SFR have unrestricted read access. POR, EWT, WDIF and RWT require Timed
Access procedure to write. The remaining bits have unrestricted write accesses. Please refer TA
register discription.
TA
EG C7H
WDCON
REG D8H
CKCON
REG 8EH
MOV TA, #AAH
MOV TA, #55H
SETB WDCON.0
ORL CKCON, #11000000B
MOV TA, #AAH
MOV TA, #55H
ORL WDCON, #00000010B
; Reset watchdog timer
; Select 26 bits watchdog timer
; Enable watchdog
Accumulator
Bit:
7
6
5
4
3
2
1
0
ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0
Mnemonic: ACC
Address: E0h
ACC.7-0: The A (or ACC) register is the standard 8052 accumulator.
Extended Interrupt Enable
Bit:
7
6
5
4
3
2
1
0
-
-
-
EWDI
-
-
-
-
Mnemonic: EIE
Address: E8h
EIE.7-5: Reserved bits, will read high
EWDI: Enable Watchdog timer interrupt
B Register
Bit:
7
6
5
4
3
2
1
0
B.7
B.6
B.5
B.4
B.3
B.2
B.1
B.0
Mnemonic: B
Address: F0h
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Publication Release Date: 05/31/2004
Revision A1