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W632GG6KB Datasheet, PDF (35/159 Pages) Winbond – 16M X 8 BANKS X 16 BIT DDR3 SDRAM | |||
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W632GG6KB
8.10.1 MPR Functional Description
ï¬ One bit wide logical interface via all DQ pins during READ operation.
ï¬ Register Read:
â DQL[0] and DQU[0] drive information from MPR.
â DQL[7:1] and DQU[7:1] either drive the same information as DQL[0], or they drive 0b.
ï¬ Addressing during for Multi Purpose Register reads for all MPR agents:
â BA[2:0]: Don't care
â A[1:0]: A[1:0] must be equal to â00âb. Data read burst order in nibble is fixed
â A[2]: A[2] selects the burst order
For BL=8, A[2] must be equal to 0b, burst order is fixed to [0,1,2,3,4,5,6,7], *)
For Burst Chop 4 cases, the burst order is switched on nibble base
A[2]=0b, Burst order: 0,1,2,3 *)
A[2]=1b, Burst order: 4,5,6,7 *)
â A[9:3]: Don't care
â A10/AP: Don't care
â A12/BC#: Selects burst chop mode on-the-fly, if enabled within MR0
â A11, A13: Don't care
ï¬ Regular interface functionality during register reads:
â Support two Burst Ordering which are switched with A2 and A[1:0]=00b.
â Support of read burst chop (MRS and on-the-fly via A12/BC#)
â All other address bits (remaining column address bits including A10, all bank address bits) will
be ignored by the DDR3 SDRAM.
â Regular read latencies and AC timings apply.
â DLL must be locked prior to MPR Reads.
Note: *) Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent.
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Publication Release Date: Dec. 08, 2014
Revision: A04
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