W632GG6KB Datasheet, PDF (3/159 Pages) Winbond – 16M X 8 BANKS X 16 BIT DDR3 SDRAM

W632GG6KB
8.19.4
Asynchronous ODT Mode................................................................................................88
8.19.4.1
Synchronous to Asynchronous ODT Mode Transitions ..........................................89
8.19.4.2
8.19.4.3
Synchronous to Asynchronous ODT Mode Transition during Power-Down Entry ..89
Asynchronous to Synchronous ODT Mode Transition during Power-Down Exit.....92
8.19.4.4
Asynchronous to Synchronous ODT Mode during short CKE high and short CKE
low periods 93
9.
9.1
9.2
9.3
OPERATION MODE ...........................................................................................................................94
Command Truth Table ........................................................................................................................94
CKE Truth Table .................................................................................................................................96
Simplified State Diagram.....................................................................................................................97
10.
ELECTRICAL CHARACTERISTICS ...................................................................................................98
10.1 Absolute Maximum Ratings ................................................................................................................98
10.2 Operating Temperature Condition.......................................................................................................98
10.3 DC & AC Operating Conditions ...........................................................................................................98
10.3.1
Recommended DC Operating Conditions ........................................................................98
10.4 Input and Output Leakage Currents ....................................................................................................99
10.5 Interface Test Conditions ....................................................................................................................99
10.6 DC and AC Input Measurement Levels.............................................................................................100
10.6.1
10.6.2
DC and AC Input Levels for Single-Ended Command and Address Signals..................100
DC and AC Input Levels for Single-Ended Data Signals................................................101
10.6.3
10.6.4
Differential swing requirements for clock (CK - CK#) and strobe (DQS - DQS#) ...........103
Single-ended requirements for differential signals .........................................................104
10.6.5
10.6.6
Differential Input Cross Point Voltage ............................................................................105
Slew Rate Definitions for Single-Ended Input Signals....................................................106
10.6.7
Slew Rate Definitions for Differential Input Signals ........................................................106
10.7 DC and AC Output Measurement Levels ..........................................................................................107
10.7.1
Output Slew Rate Definition and Requirements .............................................................107
10.7.1.1
Single Ended Output Slew Rate ...........................................................................108
10.7.1.2
Differential Output Slew Rate ...............................................................................109
10.8 34 ohm Output Driver DC Electrical Characteristics..........................................................................110
10.8.1
Output Driver Temperature and Voltage sensitivity........................................................112
10.9 On-Die Termination (ODT) Levels and Characteristics .....................................................................113
10.9.1
10.9.2
ODT Levels and I-V Characteristics ...............................................................................113
ODT DC Electrical Characteristics .................................................................................114
10.9.3
ODT Temperature and Voltage sensitivity .....................................................................114
10.9.4
Design guide lines for RTTPU and RTTPD .......................................................................115
10.10
ODT Timing Definitions............................................................................................................116
10.10.1
Test Load for ODT Timings ............................................................................................116
10.10.2
ODT Timing Definitions ..................................................................................................116
10.11
Input/Output Capacitance ........................................................................................................120
10.12
Overshoot and Undershoot Specifications...............................................................................121
10.12.1
AC Overshoot /Undershoot Specification for Address and Control Pins: .......................121
10.12.2
AC Overshoot /Undershoot Specification for Clock, Data, Strobe and Mask pins:.........121
10.13
IDD and IDDQ Specification Parameters and Test Conditions ................................................122
10.13.1
IDD and IDDQ Measurement Conditions .......................................................................122
10.13.2
IDD Current Specifications .............................................................................................132
10.14
Clock Specification ..................................................................................................................133
10.15
Speed Bins ..............................................................................................................................134
10.15.1
DDR3-1333 Speed Bin and Operating Conditions .........................................................134
10.15.2
DDR3-1600 Speed Bin and Operating Conditions .........................................................135
Publication Release Date: Dec. 08, 2014
Revision: A04
-3-