W632GG6KB Datasheet, PDF (106/159 Pages) Winbond – 16M X 8 BANKS X 16 BIT DDR3 SDRAM

W632GG6KB
Table 22 – Cross point voltage for differential input signals (CK, DQS)
PARAMETER
Differential Input Cross Point Voltage
relative to VDD/2 for CK, CK#
Differential Input Cross Point Voltage
relative to VDD/2 for DQS, DQS#
SYMBOL
VIX(CK)
DDR3-1333, DDR3-1600 & DDR3-1866
MIN.
MAX.
- 150
150
- 175
175
VIX(DQS)
-150
150
UNIT NOTES
mV
2
mV
1
mV
2
Note:
1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CK and CK# are monotonic with
a single-ended swing VSEL/VSEH of at least VDD/2 ± 250 mV, and when the differential slew rate of CK - CK# is larger
than 3 V/nS. Refer to Table 21 for VSEL and VSEH standard values.
2. The relation between VIX Min/Max and VSEL/VSEH should satisfy following.
(VDD/2) + VIX (Min) - VSEL ≥ 25mV
VSEH - ((VDD/2) + VIX (Max)) ≥ 25mV
10.6.6 Slew Rate Definitions for Single-Ended Input Signals
See section 10.16.4 “Address / Command Setup, Hold and Derating” on page 149 for single-
ended slew rate definitions for address and command signals.
See section 10.16.5 “Data Setup, Hold and Slew Rate Derating” on page 156 for single-ended slew
rate definitions for data signals.
10.6.7 Slew Rate Definitions for Differential Input Signals
Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and measured as shown
in Table 23 and Figure 93.
Table 23 – Differential Input Slew Rate Definition
Description
Differential input slew rate for rising edge
(CK - CK# and DQS - DQS#)
Differential input slew rate for falling edge
(CK - CK# and DQS - DQS#)
Measured
from
to
VIL.DIFFmax VIH.DIFFmin
VIH.DIFFmin VIL.DIFFmax
Defined by
[VIH.DIFFmin - VIL.DIFFmax] / ΔTR.DIFF
[VIH.DIFFmin - VIL.DIFFmax] / ΔTF.DIFF
Note: The differential signal (i.e., CK - CK# and DQS - DQS#) must be linear between these thresholds
ΔTR.DIFF
VIH.DIFFmin
0
VIL.DIFFmax
ΔTF.DIFF
Figure 93 – Differential Input Slew Rate Definition for DQS, DQS# and CK, CK#
- 106 -
Publication Release Date: Dec. 08, 2014
Revision: A04