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W632GG6KB Datasheet, PDF (155/159 Pages) Winbond – 16M X 8 BANKS X 16 BIT DDR3 SDRAM | |||
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W632GG6KB
Note: Clock and Strobe are drawn
on a different time scale.
tIS
tIH
CK
CK#
DQS#
DQS
tDS
tDH
VDDQ
tIS
tIH
tDS
tDH
VIH(AC)min
VIH(DC)min
DC to VREF
region
VREF(DC)
VIL(DC)max
DC to VREF
region
VIL(AC)max
tangent
line
nominal
line
tangent
line
nominal
line
VSS
ÎTR
Hold Slew Rate tangent line [VREF(DC) - VIL(DC)max]
Rising Signal =
ÎTR
ÎTF
Hold Slew Rate tangent line [VIH(DC)min - VREF(DC)]
Falling Signal =
ÎTF
Figure 110 â Illustration of tangent line for for hold time tDH (for DQ with respect to strobe) and
tIH (for ADD/CMD with respect to clock)
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Publication Release Date: Dec. 08, 2014
Revision: A04
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