W78E378 Datasheet, PDF (32/38 Pages) Winbond – MONITOR MICROCONTROLLER

Preliminary W78E378/W78C378/W78C374
Reset Circuit- Power-low Detector & Watchdog Timer
The reset signals come from the following three sources:
1. External reset input (active low)
2. Power low detect
3. Hardware Watchdog Timer
The power-low detection circuit generates a reset signal once the VCC falls below 3.5V for above 10
µS or falls below 1.8V, and the reset signal is released after VCC goes up to 4.3V.
4.3V
3.8V
1.8V
VCC
Power-low Reset
10uS
The purpose of a watchdog timer is to reset the CPU if the user program fails to reload the watchdog
timer within a reasonable period of time known as the "watchdog interval". The clock source of the
watchdog timer comes from the internal system clock. It can be enabled/disabled by set/clear
WDTEN (bit 5 of CTRL2). For debug purpose, if the WDT reset or power low reset occur, the RESET
pin will be pulled low internally. The pulled-low duration due to WDT reset is about 60/Fosc sec. The
block diagram of the reset circuitry is shown as below.
R:100K
/RESET
C:0.01u
External Reset
Watchdog
Timer
EN
WDTEN
Power-low
Supervisor
Reset Logic
Iol=12mA @Vol=0.45V
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