W78E378 Datasheet, PDF (27/38 Pages) Winbond – MONITOR MICROCONTROLLER

Preliminary W78E378/W78C378/W78C374
Sync Processor
Polarity Detector
The H/V polarity is detected automatically and can be known from HPOL bit (HFCOUNTH.7) and
VPOL bit (VFCOUNTH.7).
Fosc
Max. H+V width
Max. V width
10 MHz
(64/Fosc) × 62 (counter overflow) = 396.8 µS
(2048/Fosc) × 2 = 409.6 µS
Sync Separator
The Vsync is separated from the composite sync automatically, without any software effort.
Fosc
Min. V width & Max. H width
10 MHz
(1/Fosc) × 64 = 6.4 µS
Horizontal & Vertical Frequency Counter
There are two 12-bit counters which can count H and V frequency automatically. When VEVENT
(Vsync frequency counter timeout) interrupt happens, the count value values are latched into the
counter registers (HFCOUNTH, HFCOUNTL, VFCOUNTH and VFCOUNTL). And then the S/W may
read the count value (H_COUNT and V_COUNT) from the counter registers to calculate the H and V
frequency by the formulas listed below.
V frequency:
The resolution of V frequency counter: VRESOL = (1/Fosc) × 64.
The V frequency: VFREQ = 1/(VCOUNT × VRESOL).
The lowest V frequency can be detected: Fosc ÷ 262144. (38.1Hz @Fosc =10 MHz)
H frequency:
The resolution of H frequency counter: HRESOL = (1/Fosc) ÷ 8.
The H frequency: HFREQ = 1/(HCOUNT × HRESOL).
The lowest H frequency can be detected: Fosc ÷ 512. (19.5 KHz @Fosc = 10 MHz)
Dummy Frequency Generator
The Dummy H and V frequencies are generated for factory burn-in or showing warning message
while there are no input frequency.
(HDUMS1, HDUMS0)
FdummyH
Hsync width
(0, 0)
Fosc/(8 × 4 × 8)
(8 × 4)/Fosc
(0, 1)
Fosc/(8 × 2 × 8)
(8 × 2)/Fosc
(1, 0)
Fosc/(8 × 3 × 8)
(8 × 3)/Fosc
(1, 1)
Fosc/(8 × 5 × 8)
(8 × 5)/Fosc
VDUMS
FdummyV
Vsync width
0
FdummyH/ 512
8/ FdummyH
1
FdummyH/1024
16/ FdummyH
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Publication Release Date: December 1999
Revision A1