W6694 Datasheet, PDF (31/33 Pages) Winbond – USB Bus ISDN S/T-Controller

Preliminary W6694
PARAMETER PARAMETER DESCRIPTIONS MIN. NOMINAL MAX. REMARKS
ta1
PBCK pulse high
325
Unit = nS
ta2
PBCK pulse low
195
325
455
ta3
Frame clock asserted from PBCK
20
ta4
PTXD data delay from PBCK
20
ta5
Frame clock deasserted from
20
PBCK
ta6
PTXD hold time from PBCK
10
ta7
PRXD setup time to PBCK
20
ta8
PRXD hold time from PBCK
10
Note: The PCM clocks are locked to the S/T receive clock. At every two or three PCM frame time (125 µS), PBCK and PFCK1,
PFCK2 may be adjusted by one local oscillator cycle (130 nS) in order to synchronize with S/T clock. This shift is made
on the LOW level time of PBCK and the HIGH level time is not affected. This introduces jitters on the PBCK, PFCK1 and
PFCK2 with jitter amplitude 260 nS (peak-to-peak) and jitter frequency about 2.67~4 KHz.
9.4.2 Serial EEPROM Timing
EPSK
EPCS
EPSDI
tb1 tb2
tb3
tb3
tb4
tb4
tb6
tb5
tb7
A5 A4 ^..... A1 A0
D15 D14 ....... D1 D0
PARAMETER
tb1
tb2
tb3
tb4
tb5
tb6
tb7
PARAMETER DESCRIPTIONS
EPSK low
EPSK high
EPCS output delay
EPSD output delay
EPSD tri-state delay
EPSD input setup time
EPSD input hold time
MIN.
2500
2500
30
30
MAX.
REMARKS
Unit = nS
30
30
30
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Publication Release Date: October 2000
Revision A1