W6694 Datasheet, PDF (24/33 Pages) Winbond – USB Bus ISDN S/T-Controller

Preliminary W6694
0: MR bit always 1. In addition, the MDR interrupt is blocked, except for the first byte of a
packet (if MRIE = 1).
1: MR internally controlled according to Monitor channel protocol. In addition, the MDR
interrupt is enabled for all bytes according to the Monitor channel protocol (if MRIE = 1).
MXIE Monitor Channel Transmit Interrupt Enable
Monitor interrupt status MDA, MAB generation is enabled (1) or masked (0).
MXC MX Bit Control
Determines the value of the MX bit:
0: MX always 1.
1: MX internally controlled according to Monitor channel protocol.
8.3.3 Monitor Channel Receive Register
MOR
Value after reset: FFh
7
6
5
4
3
2
Read
1
Address 08h
0
8.3.4 Monitor Channel Transmit Register MOX
Value after reset: FFh
7
6
5
4
3
2
Read/Write Address 09h
1
0
8.4 Programmable IO Registers
8.4.1 PIO Input Enable Register
Value after reset: 00h
7
6
5
4
IE7
IE6
IE5
IE4
PIE
Read/Write Address 0Ah
3
2
1
0
IE3
IE2
IE1
IE0
IE7-0 Input Enable for IO Pin 7-0.
Setting these bits enable corresponding IO pin to become input pin. Default is output pin.
8.4.2 PIO Output Register 1
Value after reset: FFh
7
6
5
OM3_1 OM3_0 OM2_1
4
OM2_0
PO1
3
OM1_1
Read/Write
2
1
OM1_0 OM0_1
Address 0Bh
0
OM0_0
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