W6694 Datasheet, PDF (20/33 Pages) Winbond – USB Bus ISDN S/T-Controller

Preliminary W6694
8.2.2 Command Register 1
CMDR1 Write
Address 01h
Value after reset: 00h
Writing 1 to the following bits will activate each corresponding function. Writing 0 to these bits has no
effect.
7
6
5
4
3
2
1
0
DXRST DRRST DXEN DREN SRST CISOE DLP
RLP
DXRST D Channel Transmitter Reset
Setting this bit resets D channel transmitter, and clear transmit FIFO (XFIFO). The transmitter
will immediately transmit inter frame time fill pattern (all 1’s) to D channel in ISDN layer 1, but
the XFIFO is disabled (not active). Software must issue DXEN to enable (activate) D channel
XFIFO. After reset is done, this bit becomes 0. If this bit and other bits are set at the same
time, the reset action will be performed first and completed, then other actions will follow.
DRRST D Channel Receiver Reset
Setting this bit resets D channels receiver, and clear receive FIFO (RFIFO). The D channels
is disabled (not active). Software must issue DREN to enable (activate) D channel RFIFO, in
order to receive D channel data from ISDN, and send data to USB. After reset is done, this bit
becomes 0. If this bit and other bits are set at the same time, the reset action will be
performed first and completed, then other actions will follow.
DXEN D Channel Transmit FIFO Enable
Setting this bit enables D channel transmit FIFO (XFIFO). After enabled, the D channel
XFIFO will begin to receive D channel data from USB, and send data to ISDN. After enabled,
this bit becomes 0.
DREN D Channel Receive FIFO Enable
Setting this bit enables D channel receive FIFO (RFIFO). After enabled, the D channel
RFIFO will begin to receive D channel data from ISDN, and send data to USB. After enabled,
this bit becomes 0.
SRST Software Reset
Setting this bit internally generates a software reset signal. The effect of this reset signal is
equivalent to hardware reset pin, except that the USB circuit and all USB configured data are
not reset. This bit must be set along, i.e., all other bits in this register must not set at the
same time. This bit is not auto-clear, once this bit is set to ‘1’, software must write ‘0’ to this
bit to exit from the reset mode. In the reset-mode the chip will not function properly.
CISOE Clear Isochronous-OUT Error
Setting this bit clears error indication bit ISOE of Isochronous-OUT error. This bit is carried by
Isochronous-IN packet. After bits are cleared, this bit becomes 0.
DLP
Digital Loopback
Setting this bit activates the digital loopback function. The transmitted digital 2B+D channels
are looped to the received 2B+D channels. Note that after hardware reset, the internal clocks
will turn off if the S bus is not connected or if there is no signal on the S bus. In this case, the
C/I command ECK must be issued to enable loopback function.
This bit remains set, until cleared by software reset (SRST).
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