W9425G6EH Datasheet, PDF (3/50 Pages) Winbond – 4 M × 4 BANKS × 16 BITS DDR SDRAM

W9425G6EH
10.16 Write Interrupted by Read (CL = 2, BL = 8)....................................................................... 43
10.17 Write Interrupted by Read (CL = 3, BL = 4)....................................................................... 44
10.18 Write Interrupted by Precharge (BL = 8) ........................................................................... 44
10.19 2 Bank Interleave Read Operation (CL = 2, BL = 2) ......................................................... 45
10.20 2 Bank Interleave Read Operation (CL = 2, BL = 4) ......................................................... 45
10.21 4 Bank Interleave Read Operation (CL = 2, BL = 2) ......................................................... 46
10.22 4 Bank Interleave Read Operation (CL = 2, BL = 4) ......................................................... 46
10.23 Auto Refresh Cycle............................................................................................................ 47
10.24 Precharged/Active Power Down Mode Entry and Exit Timing .......................................... 47
10.25 Input Clock Frequency Change during Precharge Power Down Mode Timing................. 47
10.26 Self Refresh Entry and Exit Timing ................................................................................... 48
11. PACKAGE SPECIFICATION ....................................................................................................... 49
11.1 TSOP 66 lI – 400 mil ......................................................................................................... 49
12. REVISION HISTORY ................................................................................................................... 50
Publication Release Date:Apr. 11, 2008
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Revision A04