W9425G6EH Datasheet, PDF (25/50 Pages) Winbond – 4 M × 4 BANKS × 16 BITS DDR SDRAM

W9425G6EH
9.5 DC Characteristics
SYM.
PARAMETER
MAX.
-4 -5
-6
Operating current: One Bank Active-Precharge; tRC = tRC
IDD0
min; tCK = tCK min; DQ, DM and DQS inputs changing twice
per clock cycle; Address and control inputs changing once
110 110 110
per clock cycle
Operating current: One Bank Active-Read-Precharge; Burst =
IDD1
2; tRC = tRC min; CL = 3; tCK = tCK min; IOUT = 0 mA; Address
and control inputs changing once per clock cycle.
150 150 150
Precharge Power Down standby current: All Banks Idle;
IDD2P Power down mode; CKE < VIL max; tCK = tCK min; Vin = VREF 20
20
20
for DQ, DQS and DM
Idle floating standby current: CS > VIH min; All Banks Idle;
IDD2F _{CKE > VIH min; Address and other control inputs changing}
45 45 45
once per clock cycle; Vin = Vref for DQ, DQS and DM
IDD2N
Idle standby current: CS > VIH min; All Banks Idle; CKE >
VIH min; tCK = tCK min; Address and other control inputs
changing once per clock cycle; Vin > VIH min or Vin < VIL
max for DQ, DQS and DM
45 45 45
Idle quiet standby current: CS > VIH min; All Banks Idle;
IDD2Q _{CKE > VIH min; tCK = tCK min; Address and other control}
40 40 40
inputs stable; Vin > VREF for DQ, DQS and DM
IDD3P
Active Power Down standby current: One Bank Active; Power
down mode; CKE < VIL max; tCK = tCK min
20
20
20
Active standby current: CS > VIH min; CKE > VIH min; One
IDD3N ^{Bank Active-Precharge; tRC = tRAS max; tCK = tCK min; DQ,}
70 70 70
DM and DQS inputs changing twice per clock cycle; Address
and other control inputs changing once per clock cycle
IDD4R
Operating current: Burst = 2; Reads; Continuous burst; One
Bank Active; Address and control inputs changing once per
clock cycle; CL=3; tCK = tCK min; IOUT = 0mA
210 180 170
Operating current: Burst = 2; Write; Continuous burst; One
IDD4W
Bank Active; Address and control inputs changing once per
clock cycle; CL = 3; tCK = tCK min; DQ, DM and DQS inputs
changing twice per clock cycle
210 180 170
IDD5 Auto Refresh current: tRC = tRFC min
190 190 190
IDD6 Self Refresh current: CKE < 0.2V
3
3
3
Random Read current: 4 Banks Active Read with activate
IDD7
every 20nS, Auto-precharge Read every 20 nS; Burst = 4;
tRCD = 3; IOUT = 0mA; DQ, DM and DQS inputs changing
300 300 300
twice per clock cycle; Address changing once per clock cycle
UNIT NOTES
-75
110
7
150
7, 9
20
40
7
40
7
35
7
mA
20
65
7
160
7, 9
160
7
190
7
3
300
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Publication Release Date:Apr. 11, 2008
Revision A04