W93910 Datasheet, PDF (3/35 Pages) Winbond – ERMES PAGING DECODER

W93910
Pin Description, continued
SYMBOL PIN
TXCLK
12
TXDATA
13
ON
14
XRST
15
PTEST
16
CHRS
17
XCNCG
18
SYNVAL
19
ADRDET
20
MSGVAL
21
MDATA
22
MCLK
23
ENLED
24
TEST1
25
TEST2
26
LEDO
27
VDD
28
I/O
PIN DESCRIPTION
I 192 option bits clock input from µC. TXDATA will be latched by
W93910 during TXCLK rising edge.
I/O 192 option bits serial data input from µC. Option bit address will be
increased by one after each TXCLK period. After 192 option setting,
the TXDATA pin will change to output pin for received OPID
information access.
I Active high to enable W93910 chip operating. Oscillator starts
oscillation after ON rising edge. OSCO will always stop while ON is
low.
I Internal pull low, Active high to reset decoder.
I Internal pull low, Test mode only.
I Force roaming control pin. Connect to GND for normal operation. Pull
high is only for test purpose.
O During PLEN pin high level, XCNCG (eXternal ChaNnel ChanGe)
rising edge will inform µC to change channel according to channel
scanning rule.
O Synchronization Indicator (out-of-range indicator output). Output low
when synchronized with paging system.
O Active high while the user IA detected in the address partition.
(normally Low)
O MSGVAL will be active during MCLK, MDATA available period. Active
high/low is dependent on MSGI option bit.
O Serial paging message output to µC. Rising/falling edge is dependent
on MCKEG option bit. UDI1−0 used to select interval per bytes
MDATA.
O Serial clock output to µC for available paging message. MCKI used to
select initial state, and MCK1, MCK0 used to select clock rate.
I Internal pull low, Active high to enable LEDO output.
I Test only. No connection for normal operation
O Test only. No connection for normal operation
O 10/4 kHz or 40/16 kHz CMOS clock output.
I 3 volts power supply.
Publication Release Date: Auguest 1999
-3-
Revision A1