W25P022A Datasheet, PDF (3/17 Pages) Winbond – 64K X 32 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM

W25P022A
PIN DESCRIPTION
SYMBOL
TYPE
A0−A15
I/O1−I/O32
CLK
Input, Synchronous
I/O, Synchronous
Input, Clock
CE1 , CE2, CE3 ^{Input, Synchronous}
GW
BWE
BW1 − BW4
Input, Synchronous
Input, Synchronous
Input, Synchronous
OE
ADV
ADSC
ADSP
ZZ
FT
Input, Asynchronous
Input, Synchronous
Input, Synchronous
Input, Synchronous
Input, Asynchronous
Input, Static
LBO
Input, Static
MS
Input, Static
VDDQ
VSSQ
VDD
VSS
NC
DESCRIPTION
Host Address
Data Inputs/Outputs
Processor Host Bus Clock
Chip Enables
Global Write
Byte Write Enable from Cache Controller
Host Bus Byte Enables used with BWE
Output Enable Input
Internal Burst Address Counter Advance
Address Status from chip set
Address Status from CPU
Snooze Pin for Low-power State, internally pulled low
Connected to VSSQ: Device operates in flow-through
(non-pipelined) mode.
Connected to VDDQ or unconnected: Device operates
in piplined mode.
Lower Address Burst Order
Connected to VSSQ: Device operates in linear mode.
Connected to VDDQ or unconnected: Device is in non-
linear mode.
Mode Select for 2T/2T or 2T/1T
When unconnected or pulled low, device is in 2T/1T
mode; if pulled high (VDDQ), device enters 2T/2T
mode.
I/O Power Supply
I/O Ground
Power Supply
Ground
No Connection
Publication Release Date: September 1996
-3-
Revision A1