W9864G2GH Datasheet, PDF (27/46 Pages) Winbond – 512K X 4 BANKS X 32BITS SDRAM

W9864G2GH
11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)
CLK
(CLK = 100 MHz)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CS
tRC
RAS
CAS
tRAS
tRP
tRP
tRAS
tRAS
WE
BS0
BS1
A10
RAa
tRCD
tRCD
RBb
tRCD
RAc
A0-A9 ^RAa
DQM
CKE
DQ
Bank #0 ^Active
Bank #1
Bank #2
Idle
Bank #3
CAx
RBb
CBy
RAc
CAz
tRRD
tAC
tAC
ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1
tRRD
tAC
by4 by5 by6 by7
CZ0
Read
Precharge
Active
Precharge
Read
Active
Read
Precharge
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Publication Release Date:Aug. 13, 2007
Revision A09