W9864G2GH Datasheet, PDF (19/46 Pages) Winbond – 512K X 4 BANKS X 32BITS SDRAM

W9864G2GH
7. Transition times are measured between VIH and VIL.
8. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to
output level.
9. These parameters account for the number of clock cycles and depend on the operating frequency
of the clock, as follows the number of clock cycles = specified value of timing/ clock period (count
fractions as whole number)
(1)tCH is the pulse width of CLK measured from the positive edge to the negative edge referenced to VIH (min.).
tCL is the pulse width of CLK measured from the negative edge to the positive edge referenced to VIL (max.).
(2)A.C Latency Characteristics
CKE to clock disable (CKE Latency)
DQM to output to HI-Z (Read DQM Latency)
DQM to output to HI-Z (Write DQM Latency)
Write command to input data (Write Data Latency)
CS to Command input ( CS Latency)
Precharge to DQ Hi-Z Lead time
Precharge to Last Valid data out
Bust Stop Command to DQ Hi-Z Lead time
Bust Stop Command to Last Valid Data out
Read with Auto-precharge Command to Active/Ref Command
Write with Auto-precharge Command to Active/Ref Command
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
1
2
0
0
0
2
3
1
2
2
3
1
2
BL + tRP
BL + tRP
(BL+1) + tRP
(BL+1) + tRP
tCK
tCK + nS
10. Assumed input rise and fall time (t_T ) = 1nS.
If tr & tf is longer than 1nS, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]nS should be added to the parameter
( The t_T maximum can’t be more than 10nS for low frequency application. )
11. If clock rising time (t_T) is longer than 1nS, (t_T/2-0.5)nS should be added to the parameter.
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Publication Release Date:Aug. 13, 2007
Revision A09