W9464G6IB Datasheet, PDF (26/51 Pages) Winbond – 1M × 4 BANKS × 16 BITS DDR SDRAM

W9464G6IB
9.5 DC Characteristics
SYM.
PARAMETER
IDD0
Operating current: One Bank Active-Precharge;
tRC = tRC min; tCK = tCK min;
DQ, DM and DQS inputs changing once per clock cycle;
Address and control inputs changing once every two clock cycles
IDD1
IDD2P
IDD2N
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
Operating current: One Bank Active-Read-Precharge;
Burst = 4; tRC = tRC min; CL = 3; tCK = tCK min; IOUT = 0 mA;
Address and control inputs changing once per clock cycle
Precharge Power Down standby current:
All Banks Idle; Power down mode;
CKE < VIL max; tCK = tCK min; Vin = VREF for DQ, DQS and DM
Idle standby current:
CS > VIH min; All Banks Idle; CKE > VIH min; tCK = tCK min;
Address and other control inputs changing once per clock cycle;
Vin > VIH min or Vin < VIL max for DQ, DQS and DM
Idle floating standby current:
CS > VIH min; All Banks Idle; CKE > VIH min;
Address and other control inputs changing once per clock cycle;
Vin = VREF for DQ, DQS and DM
Idle quiet standby current:
CS > VIH min; All Banks Idle; CKE > VIH min; tCK = tCK min;
Address and other control inputs stable;
Vin = VREF for DQ, DQS and DM
Active Power Down standby current:
One Bank Active; Power down mode;
CKE < VIL max; tCK = tCK min;
Vin = VREF for DQ, DQS and DM
Active standby current:
CS > VIH min; CKE > VIH min; One Bank Active-Precharge;
tRC = tRAS max; tCK = tCK min;
DQ, DM and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per clock cycle
Operating current:
Burst = 2; Reads; Continuous burst; One Bank Active;
Address and control inputs changing once per clock cycle;
CL=2; tCK = tCK min; IOUT = 0mA
Operating current:
Burst = 2; Write; Continuous burst; One Bank Active;
Address and control inputs changing once per clock cycle;
CL = 2; tCK = tCK min;
DQ, DM and DQS inputs changing twice per clock cycle
Auto Refresh current: tRC = tRFC min
Self Refresh current: CKE < 0.2V; external clock on; tCK = tCK min
Random Read current: 4 Banks Active Read with activate every 20nS,
Auto-Precharge Read every 20 nS;
Burst = 4; tRCD = 3; IOUT = 0mA;
DQ, DM and DQS inputs changing twice per clock cycle;
Address changing once per clock cycle
MAX.
-5
UNIT NOTES
120
7
140
7, 9
20
50
50
7
50
7
mA
30
60
7
185
7, 9
180
7
210
7
2.5
320
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Publication Release Date:Oct. 16, 2008
Revision A01