W9464G6IB Datasheet, PDF (16/51 Pages) Winbond – 1M × 4 BANKS × 16 BITS DDR SDRAM

W9464G6IB
7.10.3 CAS Latency field (A6 to A4)
This field specifies the number of clock cycles from the assertion of the Read command to the first
data read. The minimum values of CAS Latency depend on the frequency of CLK.
A6
A5
A4
CAS LATENCY
0
0
0
Reserved
0
0
1
Reserved
0
1
0
2
0
1
1
3
1
0
0
Reserved
1
0
1
Reserved
1
1
0
2.5
1
1
1
Reserved
7.10.4 DLL Reset bit (A8)
This bit is used to reset DLL. When the A8 bit is “1”, DLL is reset.
7.10.5 Mode Register/Extended Mode register change bits (BA0, BA1)
These bits are used to select MRS/EMRS.
BA1
BA0
0
0
0
1
1
x
A11-A0
Regular MRS Cycle
Extended MRS Cycle
Reserved
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Publication Release Date:Oct. 16, 2008
Revision A01